公开(公告)号：US11942334B2

公开(公告)日：2024-03-26

申请号：US16231181

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Suddhasattwa Nad ,  Kristof Kuwawi Darmawikarta ,  Vahidreza Parichehreh ,  Veronica Aleman Strong ,  Xiaoying Guo

IPC: H05K1/02 ,  H01L21/027 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L21/4846 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H05K1/0218 ,  H01L2224/16225

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

公开(公告)号：US11373951B2

公开(公告)日：2022-06-28

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US11721631B2

公开(公告)日：2023-08-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US11506982B2

公开(公告)日：2022-11-22

申请号：US16143206

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Vahidreza Parichehreh ,  Keith J. Martin ,  Changhua Liu ,  Leonel Arana

IPC: G03F7/20 ,  H01L21/027 ,  G02B5/04 ,  H01L21/3213

Abstract: Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. The lithographic patterning system includes an actinic radiation source, a stage having a surface for supporting a substrate with a resist layer, and a prism with a first surface over the stage, where the first surface has a masked layer and is substantially parallel to the surface of the stage. The prism may have a second surface that is substantially parallel to the first surface. The first and second surfaces are flat surfaces. The prism is a monolithic prism-mask, where an optical path passes through the system and exits the first surface of the prism through the mask layer. The system may include a layer disposed between the mask and resist layers. The mask layer of the prism may pattern the resist layer without an isolated mask layer.

公开(公告)号：US10910327B2

公开(公告)日：2021-02-02

申请号：US16369681

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Yonggang Li ,  Brandon C Marin ,  Vahidreza Parichehreh ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.

公开(公告)号：US20200312787A1

公开(公告)日：2020-10-01

申请号：US16369681

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Yonggang Li ,  Brandon C. Marin ,  Vahidreza Parichehreh ,  Jeremy D. Ecton

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.

公开(公告)号：US20190304912A1

公开(公告)日：2019-10-03

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.