公开(公告)号：US11164785B2

公开(公告)日：2021-11-02

申请号：US16728903

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC: H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.

公开(公告)号：US11101377B2

公开(公告)日：2021-08-24

申请号：US15939087

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Gilbert Dewey ,  Van H. Le ,  Willy Rachmady ,  Ravi Pillarisetty

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/267

Abstract: Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.

公开(公告)号：US11075202B2

公开(公告)日：2021-07-27

申请号：US16650155

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

公开(公告)号：US11017843B2

公开(公告)日：2021-05-25

申请号：US16457617

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gilbert Dewey ,  Willy Rachmady ,  Van Le ,  Matthew Metz ,  Jack Kavalieros

IPC: G11C11/24 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4094 ,  G11C11/408

Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.

公开(公告)号：US20210074702A1

公开(公告)日：2021-03-11

申请号：US16642356

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Van H. Le ,  Marko Radosavljevic ,  Han Wui Then ,  Willy Rachmady ,  Ravi Pillarisetty ,  Abhishek Sharma ,  Gilbert Dewey ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8258

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

公开(公告)号：US10930679B2

公开(公告)日：2021-02-23

申请号：US16461701

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek A. Sharma ,  Shriram Shivaraman ,  Van H. Le ,  Ravi Pillarisetty ,  Tahir Ghani

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/22 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/49

Abstract: Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.

公开(公告)号：US10886408B2

公开(公告)日：2021-01-05

申请号：US16327206

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Willy Rachmady ,  Anand S. Murthy ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L29/20 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/26 ,  H01L21/8252 ,  H01L29/16

Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.

公开(公告)号：US20200273962A1

公开(公告)日：2020-08-27

申请号：US16649933

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Prashant Majhi ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L27/22 ,  H01L27/24 ,  H01L29/49

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

公开(公告)号：US20200258881A1

公开(公告)日：2020-08-13

申请号：US16649712

申请日：2018-01-18

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/861 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66

Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

公开(公告)号：US10734511B2

公开(公告)日：2020-08-04

申请号：US16077742

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Rafael Rios

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/739 ,  H01L29/08

Abstract: An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.