公开(公告)号：US20220199838A1

公开(公告)日：2022-06-23

申请号：US17133056

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching LIn ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/786 ,  H01L29/06 ,  H01L23/29 ,  H01L21/8238

Abstract: A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

公开(公告)号：US11362263B2

公开(公告)日：2022-06-14

申请号：US16024411

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Justin Brockman ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  B82Y25/00

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.

公开(公告)号：US11227644B2

公开(公告)日：2022-01-18

申请号：US15942086

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Noriyuki Sato ,  Kaan Oguz ,  Mark Doczy ,  Charles Kuo

IPC: G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  B82Y25/00

Abstract: A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.

公开(公告)号：US20200006630A1

公开(公告)日：2020-01-02

申请号：US16024393

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Gary Allen ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young ,  Ben Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

公开(公告)号：US20240222441A1

公开(公告)日：2024-07-04

申请号：US18091197

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Carl Naylor ,  Chelsey Dorow ,  Chia-Ching Lin ,  Dominique Adams ,  Kevin O'Brien ,  Matthew Metz ,  Scott Clendenning ,  Sudarat Lee ,  Tristan Tronic ,  Uygar Avci

IPC: H01L29/40 ,  H01L21/04 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/44 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/043 ,  H01L21/044 ,  H01L21/28264 ,  H01L21/32136 ,  H01L21/44 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/454 ,  H01L29/78648 ,  H01L29/4908

Abstract: Devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2D materials for transistor devices. A transistor structure includes a gate dielectric structure on a 2D semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2D semiconductor material layer. The source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.

公开(公告)号：US11594673B2

公开(公告)日：2023-02-28

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Benjamin Buford ,  Tofizur Rahman ,  Rohan Patil ,  Nafees Kabir ,  Michael Christenson ,  Ian Young ,  Hui Jae Yoo ,  Christopher Wiegand

IPC: H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US11476412B2

公开(公告)日：2022-10-18

申请号：US16012672

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/04 ,  H01L43/10 ,  H01L43/08 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32 ,  B82Y25/00

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.

公开(公告)号：US20220199812A1

公开(公告)日：2022-06-23

申请号：US17129486

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Sudarat Lee ,  Kirby Maxey ,  Ashish Verma Penumatcha ,  Tanay Gosavi ,  Patrick Theofanis ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Shriram Shivaraman

IPC: H01L29/76 ,  H01L29/24 ,  H01L27/092 ,  H01L21/8256 ,  H01L21/02

Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

公开(公告)号：US11367749B2

公开(公告)日：2022-06-21

申请号：US16022564

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Atm G. Sarwar ,  Ian Young ,  Hui Jae Yoo ,  Christopher Wiegand ,  Benjamin Buford

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12 ,  H01F41/34

Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.

公开(公告)号：US11348970B2

公开(公告)日：2022-05-31

申请号：US15960218

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Benjamin Buford ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/04 ,  H01L45/00 ,  B82Y25/00

Abstract: A spin orbit torque (SOT) memory device includes an SOT electrode on an upper end of an MTJ device. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet and is coupled with a conductive interconnect at a lower end of the MTJ device. The SOT electrode has a footprint that is substantially the same as a footprint of the MTJ device. The SOT device includes a first contact and a second contact on an upper surface of the SOT electrode. The first contact and the second contact are laterally spaced apart by a distance that is no greater than a length of the MTJ device.