公开(公告)号：US09692756B2

公开(公告)日：2017-06-27

申请号：US14864572

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： David I. Poisner ,  Gregory A. Peek ,  Blanka Vlasak ,  Yevgeniy Y. Yarmosh ,  Mark R. Francis ,  Ravishankar Iyer

IPC: H04L29/06

CPC classification number: H04L63/0861 ,  A63F13/211 ,  A63F13/235 ,  A63F13/35 ,  A63F13/428 ,  A63F13/71 ,  A63F13/92 ,  A63F13/98 ,  H04L63/10

Abstract: Methods, apparatuses, systems, and storage media for creating, discovering, and/or resolving spells using a wand are provided. In embodiments, a computing device or a wand may detect one or more gestures and sensors in the wand may generate sensor data representative of the one or more gestures. The one or more gestures may be movements performed using the wand. The sensor data representative of the one or more gestures may be converted into a spell sequence. The wand may transmit the spell sequence to a computing device, and receive, from the computing device, an authentication spell output when the spell sequence corresponds with an authentication spell sequence or an inactivation spell output when the spell sequence does not correspond with the authentication spell sequence. Other embodiments may be described and/or claimed.

公开(公告)号：US09639372B2

公开(公告)日：2017-05-02

申请号：US13730565

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

公开(公告)号：US20170092994A1

公开(公告)日：2017-03-30

申请号：US14866286

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Dwayne E. Canfield ,  Ravishankar Iyer ,  Andrew W. Keates ,  Gregory A. Peek ,  Mark C. Pontarelli

IPC: H01M10/42 ,  H01M10/48

CPC classification number: H01M10/4257 ,  H01M2/0202 ,  H01M2/30 ,  H01M10/0436 ,  H01M10/0562 ,  H01M10/0565 ,  H01M10/425 ,  H01M10/48 ,  H01M10/486 ,  H01M2010/4271 ,  H01M2010/4278 ,  H01M2220/30 ,  H01M2300/0065

Abstract: A battery includes integrated circuitry. The battery may include, for example, a substrate with a battery cell including an anode and a cathode. One or more electrical devices may be integrated on or within the substrate and configured to receive power from the anode and cathode. A package containing the substrate and the one or more electrical devices may include a first battery terminal electrically coupled to the anode and a second battery terminal electrically coupled to the cathode. The one or more electrical devices may include sensing circuitry to generate sensor data, and communication circuitry to provide the sensor data external to the package.

公开(公告)号：US09563564B2

公开(公告)日：2017-02-07

申请号：US14680287

申请日：2015-04-07

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher C. Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret L. Toll

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/604

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract translation: 具有代码和数据优先级的缓存分配的系统和方法。 示例系统可以包括：高速缓存; 处理核心，可操作地耦合到高速缓存; 以及高速缓存控制逻辑，响应于接收到包括请求类型的标识符和服务等级的标识符的高速缓存填充请求，以识别对应于与请求类型和类别相关联的容量位掩码的高速缓存的子集 的服务。

公开(公告)号：US20160299558A1

公开(公告)日：2016-10-13

申请号：US15134756

申请日：2016-04-21

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadogopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/24

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/5094 ,  G06F12/084 ,  G06F13/24 ,  G06F2212/1028 ,  G06F2212/60 ,  G06F2212/62 ,  H04W52/028 ,  H04W88/02 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D70/00

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

公开(公告)号：US09201500B2

公开(公告)日：2015-12-01

申请号：US13631309

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Sadagopan Srinivasan ,  Rameshkumar Illikkal ,  Ravishankar Iyer

IPC: G09G5/00 ,  G06F3/01 ,  G06F3/03

CPC classification number: G06F3/013 ,  G06F3/017 ,  G06F3/0304

Abstract: Systems and methods may provide for capturing a user input by emulating a touch screen mechanism. In one example, the method may include identifying a point of interest on a front facing display of the device based on gaze information associated with a user of the device, identifying a hand action based on gesture information associated with the user of the device, and initiating a device action with respect to the front facing display based on the point of interest and the hand action.

Abstract translation: 系统和方法可以通过仿真触摸屏机构来提供用于捕获用户输入的功能。 在一个示例中，该方法可以包括基于与设备的用户相关联的凝视信息来识别设备的正面显示器上的兴趣点，基于与设备的用户相关联的手势信息识别手动操作，以及 基于感兴趣的点和手的动作来启动相对于面向前显示器的设备动作。

公开(公告)号：US09047171B2

公开(公告)日：2015-06-02

申请号：US13631894

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Zhen Fang ,  Shih-Lien Lu ,  Ravishankar Iyer ,  Srihari Makineni

IPC: G06F12/00 ,  G06F11/00 ,  G06F1/32 ,  G11C5/14

CPC classification number: G06F11/004 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C5/141 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.

Abstract translation: 系统和方法可以提供确定存储器访问请求是否是容错的，以及如果存储器访问请求是容错的，则将存储器访问请求路由到可靠的存储器区域。 此外，如果存储器访问请求是容错的，则存储器访问请求可以被路由到不可靠的存储器区域。 在一个示例中，使用不可靠的存储区域使得能够降低包含可靠和不可靠的存储器区域的管芯的最小工作电压电平。

公开(公告)号：US20150095675A1

公开(公告)日：2015-04-02

申请号：US14564436

申请日：2014-12-09

Applicant: INTEL CORPORATION

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/32

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。

公开(公告)号：US12243157B2

公开(公告)日：2025-03-04

申请号：US18610369

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US12210434B2

公开(公告)日：2025-01-28

申请号：US16914305

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Bin Li ,  Ren Wang ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Yipeng Wang ,  Ravishankar Iyer ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Zhu Zhou ,  Rasika Subramanian

IPC: G06F11/34 ,  G06F9/50 ,  G06F18/21 ,  G06N20/00

Abstract: An apparatus and method for closed loop dynamic resource allocation. For example, one embodiment of a method comprises: collecting data related to usage of a plurality of resources by a plurality of workloads over one or more time periods, the workloads including priority workloads associated with one or more guaranteed performance levels and best effort workloads not associated with guaranteed performance levels; analyzing the data to identify resource reallocations from one or more of the priority workloads to one or more of the best effort workloads in one or more subsequent time periods while still maintaining the guaranteed performance levels; reallocating the resources from the priority workloads to the best effort workloads for the subsequent time periods; monitoring execution of the priority workloads with respect to the guaranteed performance level during the subsequent time periods; and preemptively reallocating resources from the best effort workloads to the priority workloads during the subsequent time periods to ensure compliance with the guaranteed performance level and responsive to detecting that the guaranteed performance level is in danger of being breached.