公开(公告)号：US10936490B2

公开(公告)日：2021-03-02

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/08 ,  G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US10915453B2

公开(公告)日：2021-02-09

申请号：US15394550

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Israel Diamand ,  Zvika Greenfield ,  Julius Mandelblat ,  Asaf Rubinstein

IPC: G06F12/0893 ,  G06F12/0884 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/128

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

公开(公告)号：US12198186B2

公开(公告)日：2025-01-14

申请号：US17401575

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret Toll

IPC: G06Q40/03 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

公开(公告)号：US20230018828A1

公开(公告)日：2023-01-19

申请号：US17374728

申请日：2021-07-13

Applicant: Intel Corporation

Inventor： Vadim Bassin ,  Eliezer Weissmann ,  Efraim Rotem ,  Julius Mandelblat

IPC: G06F1/3293 ,  G06F1/3228 ,  G06F9/48

Abstract: Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling. The hint indicates the given core based on a relative prioritization of the first core type and the second core type.

公开(公告)号：US20220012062A1

公开(公告)日：2022-01-13

申请号：US17482201

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Rajaram Regupathy ,  Vincent Zimmer ,  Julius Mandelblat

IPC: G06F9/4401 ,  G06F11/34

Abstract: Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

公开(公告)号：US20240202120A1

公开(公告)日：2024-06-20

申请号：US18083389

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Julius Mandelblat

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/1016

Abstract: Techniques and mechanisms for selectively configuring an integrated circuit (IC) chip to provide tag array functionality and/or cache array functionality. In an embodiment, an IC chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. Based on whether the IC chip is coupled to another IC chip, selector circuitry of the IC chip configures one of multiple possible modes of the cache controller. A first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. A second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. In another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.

公开(公告)号：US20210200656A1

公开(公告)日：2021-07-01

申请号：US16728617

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/48 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

公开(公告)号：US20210200580A1

公开(公告)日：2021-07-01

申请号：US16729370

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Julius Mandelblat ,  Eliezer Weissmann ,  Rajshree A. Chabukswar ,  Michael W. Chynoweth

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/32

Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

公开(公告)号：US20190102324A1

公开(公告)日：2019-04-04

申请号：US15721631

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Meltem Ozsoy ,  Krystof C. Zmudzinski ,  Larisa Novakovsky ,  Julius Mandelblat ,  Francis X. McKeen ,  Carlos V. Rozas ,  Ittai Anati ,  Ilya Alexandrovich

IPC: G06F12/14 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0831 ,  G06F12/0806 ,  G06F12/1027 ,  G06F12/0888 ,  G06F12/1009

Abstract: Cache behavior for secure memory repartitioning systems is described. Implementations may include a processing core and a memory controller coupled between the processor core and a memory device. The processor core is to receive a memory access request to a page in the memory device, the memory access request comprising a first guarded attribute (GA) indicator indicating whether the page is a secure page belonging to an enclave, determine whether the first GA indicator matches a second GA indicator in a cache line entry corresponding to the page, the cache line entry comprised in a cache, and responsive to a determination that the first GA indicator does not match the second GA indicator, apply an eviction policy to the cache line entry based on whether the cache line is indicated as a dirty cache line and accessing second data in the memory device for the page.

公开(公告)号：US10175992B2

公开(公告)日：2019-01-08

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F9/44 ,  G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.