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公开(公告)号：US11049266B2
公开(公告)日：2021-06-29
申请号：US16050468
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Scott Janus , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , James Holland , Narayan Biswal , Yi-Jen Chiu , Qian Xu , Mayuresh Varerkar , Sang-Hee Lee , Stanley Baran , Srikanth Potluri , Jason Ross , Maruthi Sandeep Maddipatla
Abstract: An apparatus comprises a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame.
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公开(公告)号：US11018863B2
公开(公告)日：2021-05-25
申请号：US16435083
申请日：2019-06-07
Applicant: Intel Corporation
Inventor： Balaji Vembu , Vidhya Krishnan , Sandeep S. Sodhi , Scott Janus , Daniel Nemiroff
Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号：US20210035258A1
公开(公告)日：2021-02-04
申请号：US17064427
申请日：2020-10-06
Applicant: Intel Corporation
Inventor： Joydeep Ray , Scott Janus , Varghese George , Subramaniam Maiyuran , Altug Koker , Abhishek Appu , Prasoonkumar Surti , Vasanth Ranganathan , Andrei Valentin , Ashutosh Garg , Yoav Harel , Arthur Hunter, JR. , SungYe Kim , Mike Macpherson , Elmoustapha Ould-Ahmed-Vall , William Sadler , Lakshminarayanan Striramassarma , Vikranth Vemulapalli
Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.
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公开(公告)号：US20200043182A1
公开(公告)日：2020-02-06
申请号：US16050468
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Scott Janus , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , James Holland , Narayan Biswal , Yi-Jen Chiu , Qian Xu , Mayuresh Varerkar , Sang-Hee Lee , Stanley Baran , Srikanth Potluri , Jason Ross , Maruthi Sandeep Maddipatla
Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame. Other embodiments may be described and claimed.
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公开(公告)号：US10367639B2
公开(公告)日：2019-07-30
申请号：US15394324
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Balaji Vembu , Vidhya Krishnan , Sandeep S. Sodhi , Scott Janus , Daniel Nemiroff
Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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Patent Agency Ranking
公开(公告)号：US20160162260A1
公开(公告)日：2016-06-09
申请号：US14928878
申请日：2015-10-30
Applicant: Intel Corporation
Inventor： Scott Janus
IPC: G06F3/16
CPC classification number: G06F3/167 , G06F3/048 , G06F3/1446 , G09G3/003 , H04R1/00 , H04S7/302 , H04S2400/11
Abstract: Techniques for improved audio localization for visual effects are described. In one embodiment, for example, an apparatus may comprise a processor circuit and an audio management module, and the audio management module may be operable by the processor circuit to determine a position of a user interface element in a presentation area, determine an audio effect corresponding to the user interface element, determine audio location information for the audio effect based on the position of the user interface element, the audio location information defining an apparent position for the audio effect, and generate audio playback information for the audio effect based on the audio location information. Other embodiments are described and claimed.
Abstract translation: 描述了用于改善视觉效果的音频定位的技术。 在一个实施例中，例如，设备可以包括处理器电路和音频管理模块，并且音频管理模块可以由处理器电路操作以确定用户界面元素在呈现区域中的位置，确定音频效果 对应于用户界面元素，基于用户界面元素的位置确定音频效果的音频位置信息，音频位置信息定义音频效果的明显位置，并且基于音频效果生成用于音频效果的音频回放信息 音频位置信息。 描述和要求保护其他实施例。
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公开(公告)号：US20250117356A1
公开(公告)日：2025-04-10
申请号：US18915492
申请日：2024-10-15
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Aravindh Anantaraman , Elmoustapha Ould-Ahmed-Vall , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Mike Macpherson , Subramaniam Maiyuran , Joydeep Ray , Lakshminarayanan Striramassarma , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter , Prasoonkumar Surti , David Puffer , James Valerio , Ankur N. Shah
IPC: G06F15/78 , G06F7/544 , G06F7/575 , G06F7/58 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/80 , G06F17/16 , G06F17/18 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/06 , H03M7/46
Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
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公开(公告)号：US12056059B2
公开(公告)日：2024-08-06
申请号：US17590362
申请日：2022-02-01
Applicant: Intel Corporation
Inventor： Altug Koker , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Abhishek Appu , Aravindh Anantaraman , Valentin Andrei , Durgaprasad Bilagi , Varghese George , Brent Insko , Sanjeev Jahagirdar , Scott Janus , Pattabhiraman K , SungYe Kim , Subramaniam Maiyuran , Vasanth Ranganathan , Lakshminarayanan Striramassarma , Xinmin Tian
IPC: G06F12/00 , G06F12/0875 , G06F12/0891 , G06F12/123 , G06T1/60
CPC classification number: G06F12/123 , G06F12/0875 , G06F12/0891 , G06T1/60 , G06F2212/302
Abstract: Systems and methods for cache utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.
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公开(公告)号：US11880928B2
公开(公告)日：2024-01-23
申请号：US17723772
申请日：2022-04-19
Applicant: INTEL CORPORATION
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
CPC classification number: G06T15/06 , G06T1/60 , G06T15/005 , G06T17/005 , G06T2210/21
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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公开(公告)号：US11620256B2
公开(公告)日：2023-04-04
申请号：US17732308
申请日：2022-04-28
Applicant: Intel Corporation
Inventor： Altug Koker , Joydeep Ray , Ben Ashbaugh , Jonathan Pearce , Abhishek Appu , Vasanth Ranganathan , Lakshminarayanan Striramassarma , Elmoustapha Ould-Ahmed-Vall , Aravindh Anantaraman , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Yoav Harel , Arthur Hunter, Jr. , Brent Insko , Scott Janus , Pattabhiraman K , Mike Macpherson , Subramaniam Maiyuran , Marian Alin Petre , Murali Ramadoss , Shailesh Shah , Kamal Sinha , Prasoonkumar Surti , Vikranth Vemulapalli
IPC: G06F12/08 , G06F15/78 , G06F9/30 , G06F9/38 , G06F17/18 , G06F12/0802 , G06F7/544 , G06F7/575 , G06F12/02 , G06F12/0866 , G06F12/0875 , G06F12/0895 , G06F12/128 , G06F12/06 , G06F12/1009 , G06T1/20 , G06T1/60 , H03M7/46 , G06F12/0811 , G06F15/80 , G06F17/16 , G06F7/58 , G06F12/0871 , G06F12/0862 , G06F12/0897 , G06F9/50 , G06F12/0804 , G06F12/0882 , G06F12/0891 , G06F12/0893 , G06T15/06 , G06N3/08
Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.
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