公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20200258975A1

公开(公告)日：2020-08-13

申请号：US16271639

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Rengarajan SHANMUGAM ,  Suddhasattwa NAD ,  Darko GRUJICIC ,  Srinivas PIETAMBARAM

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/66 ,  H01F27/28 ,  H01F27/24 ,  H01L25/16 ,  H01L23/552 ,  H01L21/48 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

公开(公告)号：US20200258847A1

公开(公告)日：2020-08-13

申请号：US16274086

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20200083164A1

公开(公告)日：2020-03-12

申请号：US16129711

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Frank TRUONG ,  Shivasubramanian BALASUBRAMANIAN ,  Dilan SENEVIRATNE ,  Yonggang LI ,  Sameer PAITAL ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Melissa WETTE ,  Srinivas PIETAMBARAM

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L23/00

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US20190355647A1

公开(公告)日：2019-11-21

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20240234225A1

公开(公告)日：2024-07-11

申请号：US18611534

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert L. SANKMAN ,  Rahul MANEPALLI ,  Gang DUAN ,  Debendra MALLIK

IPC: H01L23/15 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49827 ,  H01L23/5381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

公开(公告)号：US20240186197A1

公开(公告)日：2024-06-06

申请号：US18060592

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaditya Anand CANDADAI ,  Nicholas HAEHN ,  Ao WANG ,  Whitney BRYKS ,  Srinivas PIETAMBARAM

IPC: H01L23/16

CPC classification number: H01L23/16

Abstract: The present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. In an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. In yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated structures.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20240038687A1

公开(公告)日：2024-02-01

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20240021523A1

公开(公告)日：2024-01-18

申请号：US18374576

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5384 ,  H01L21/565 ,  H01L23/3107 ,  H01L25/50 ,  H01L23/562 ,  H01L21/6835 ,  H01L23/5386 ,  H01L21/486 ,  H01L21/4853 ,  H01L25/0652 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06558 ,  H01L2225/06548 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.