公开(公告)号：US20240079530A1

公开(公告)日：2024-03-07

申请号：US17903126

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Nicholas HAEHN ,  Andrea NICOLAS FLORES ,  Ali LEHAF ,  Benjamin DUONG ,  Joshua STACEY

IPC: H01L33/48 ,  H01L33/00 ,  H01L33/60 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L33/005 ,  H01L33/60 ,  H01L33/62 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

公开(公告)号：US20240070366A1

公开(公告)日：2024-02-29

申请号：US17895107

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Nicholas HAEHN ,  Raquel DE SOUZA BORGES FERREIRA ,  Siddharth ALUR ,  Prakaram JOSHI ,  Dhanya ATHREYA ,  Yidnekachew MEKONNEN ,  Ali HARIRI ,  Andrea NICOLAS ,  Sri Chaitra Jyotsna CHAVALI ,  Kemal AYGUN

IPC: G06F30/392 ,  H01L23/498

CPC classification number: G06F30/392 ,  H01L23/49838 ,  G06F2119/22 ,  H01L23/49822

Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.

公开(公告)号：US20240186197A1

公开(公告)日：2024-06-06

申请号：US18060592

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaditya Anand CANDADAI ,  Nicholas HAEHN ,  Ao WANG ,  Whitney BRYKS ,  Srinivas PIETAMBARAM

IPC: H01L23/16

CPC classification number: H01L23/16

Abstract: The present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. In an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. In yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated structures.

公开(公告)号：US20240079259A1

公开(公告)日：2024-03-07

申请号：US17901894

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Jacob VEHONSKY ,  Onur OZKAN ,  Vinith BEJUGAM ,  Mao-Feng TSENG ,  Andrea NICOLAS ,  Nicholas HAEHN

IPC: H01L21/683 ,  B32B3/30 ,  B32B7/12 ,  B32B33/00 ,  B32B37/12 ,  H01L21/67

CPC classification number: H01L21/6835 ,  B32B3/30 ,  B32B7/12 ,  B32B33/00 ,  B32B37/12 ,  H01L21/67121 ,  B32B17/06 ,  H01L2221/68345

Abstract: The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.

公开(公告)号：US20240078702A1

公开(公告)日：2024-03-07

申请号：US17902907

申请日：2022-09-05

Applicant: Intel Corporation

Inventor： Yi LI ,  Hong Seung YEON ,  Nicholas HAEHN ,  Wei LI ,  Raquel DE SOUZA BORGES FERREIRA ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN ,  Arnab ROY

IPC: G06T7/73 ,  H01L21/68 ,  H01L23/544

CPC classification number: G06T7/74 ,  H01L21/681 ,  H01L23/544 ,  G06T2207/20081 ,  G06T2207/30204 ,  H01L2223/54426

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.