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公开(公告)号：AU2003499A
公开(公告)日：1999-07-12
申请号：AU2003499
申请日：1998-12-18
Applicant: MICRON TECHNOLOGY INC
Inventor： MANNING TROY A
IPC: G11C11/407 , G06F12/00 , G11C7/10 , G11C11/401 , G11C7/00
Abstract: A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a "read" or a "write") and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and a state machine to generate command signals from the latched command bits.
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公开(公告)号：AU6685998A
公开(公告)日：1998-09-22
申请号：AU6685998
申请日：1998-03-05
Applicant: MICRON TECHNOLOGY INC
Inventor： MANNING TROY A
Abstract: A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input and output stages, each having two sets of switches. The first set of switches in each stage provides a supply voltage to a stage output in response to the asymmetrical clocks. The second set of switches supply ground to the stage output in response to the asymmetrical clocks. To accelerate response of the switching circuits, isolation switches decouple the first set of switches in each pair from the stage output during switching of the second set of switches, thereby removing loading of stage output by the second set of switches.
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公开(公告)号：DE69838852T2
公开(公告)日：2008-12-11
申请号：DE69838852
申请日：1998-10-13
Applicant: MICRON TECHNOLOGY INC
Inventor： MANNING TROY A
Abstract: A coupling circuit for coupling a first signal generated in a first circuit operating in a first clock domain to a second circuit operating in a second clock domain. The coupling circuit includes a first gate for coupling the first signal to a first logic circuit unless the coupling circuit has already applied a signal to the second circuit. The first logic circuit includes a pair of second gates that are enabled by respective rising and falling edges of the first clock signal. Thus, each of the second gates generates an output signal on respective transitions of the first clock signal as long as the first gate is coupling the first signal to the first logic circuit. The first logic circuit also includes a pair of latches coupled to respective outputs of the second gates. Each of the latches is set by its respective second gate generating the output signal. The second logic gates are coupled to a second logic circuit having a pair of third gates that are enabled by respective rising and falling edges of the second clock signal. Thus, each of the second gates generates an output signal on respective transitions of the second clock signal if the latch to which it is connected is generating an output signal. The output signal is also used as the reset signal to disable the first gate and reset the latches. Since the output signal is generated on the first transition of the first clock signal after the first signal is applied to the coupling circuit, the coupling circuit generates a single output signal that is synchronized to the second clock signal.
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公开(公告)号：AT384328T
公开(公告)日：2008-02-15
申请号：AT02797398
申请日：2002-12-18
Applicant: MICRON TECHNOLOGY INC
Inventor： JOHNSON BRIAN , KEETH BRENT , JANZEN JEFFREY W , MANNING TROY A , MARTIN CHRIS G
IPC: G01R31/28 , G11C7/22 , G11C7/10 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/14
Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
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公开(公告)号：DE602005001266T2
公开(公告)日：2008-01-24
申请号：DE602005001266
申请日：2005-01-11
Applicant: MICRON TECHNOLOGY INC
Inventor： CHOI JOO S , MANNING TROY A
Abstract: A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
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Patent Agency Ranking
公开(公告)号：DE69936865D1
公开(公告)日：2007-09-27
申请号：DE69936865
申请日：1999-06-23
Applicant: MICRON TECHNOLOGY INC
Inventor： MANNING TROY A
Abstract: A data rate control circuit that is programmable between a first data rate and a second data rate. The data rate control circuit is formed by a clocking circuit and a switching circuit. The clocking circuit receives a first clock signal on a first input line and has a second input line which receives either the second clock signal or a steady state voltage. The switching circuit selectively couples the second clock signal or the steady state voltage to the clocking circuit. When the clocking circuit receives the second clock signal, the clocking circuit clocks at a double data rate, and when the clocking circuit receives the steady state voltage, the clocking circuit clocks at a single data rate. The switching circuit includes a switch that switches the output signal between the second clock signal and the steady state voltage. The clocking circuit can be any of many circuits known to those skilled in the art including a shift register or counter latch.
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公开(公告)号：DE602005001266D1
公开(公告)日：2007-07-12
申请号：DE602005001266
申请日：2005-01-11
Applicant: MICRON TECHNOLOGY INC
Inventor： CHOI JOO S , MANNING TROY A
Abstract: A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
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公开(公告)号：AU2002312350A1
公开(公告)日：2002-12-16
申请号：AU2002312350
申请日：2002-06-06
Applicant: MICRON TECHNOLOGY INC
Inventor： KEETH BRENT , MANNING TROY A , JOHNSON BRIAN
IPC: G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C11/409 , G11C7/22
Abstract: A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with a predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.
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公开(公告)号：AT228709T
公开(公告)日：2002-12-15
申请号：AT98949381
申请日：1998-09-18
Applicant: MICRON TECHNOLOGY INC
Inventor： KEETH BRENT , MANNING TROY A
Abstract: A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi-tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.
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公开(公告)号：AT224576T
公开(公告)日：2002-10-15
申请号：AT98964787
申请日：1998-12-18
Applicant: MICRON TECHNOLOGY INC
Inventor： MANNING TROY A
IPC: G11C11/407 , G06F12/00 , G11C7/10 , G11C11/401 , G11C7/00
Abstract: A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a "read" or a "write") and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and a state machine to generate command signals from the latched command bits.
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