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    Low voltage stabilised current source
    31.
    发明专利
    Low voltage stabilised current source 未知

    公开(公告)号：GB2332760A

    公开(公告)日：1999-06-30

    申请号：GB9727166

    申请日：1997-12-24

    Applicant: MOTOROLA INC

    Inventor： NEWTON ANTHONY DAVID

    IPC: G05F3/30

    Abstract: A current source circuit produces a temperature stable current IOUT as the sum of a first current from a circuit A and a second current from a circuit B. The two currents have opposite temperature dependence. In circuit A, the base-emitter voltage of a transistor 3 is applied across a known resistor 5. The resulting current is stabilised by feedback through transistors 4,2 and then reflected into transistor 1. Circuit B includes a bandgap circuit 11-16 and output transistor 10. The device may be constructed as an integrated circuit operable at 0.9 volts, and may be used in a portable radio or mobile telephone.

    TIMEBASE CIRCUIT
    32.
    发明专利
    TIMEBASE CIRCUIT 未知

    公开(公告)号：HK22591A

    公开(公告)日：1991-04-04

    申请号：HK22591

    申请日：1991-03-26

    Applicant: MOTOROLA INC

    Inventor： JOBLING DAVID TREVOR ,  NEWTON ANTHONY DAVID

    IPC: H03K4/50 ,  H03K4/10 ,  H03K4/90 ,  H04N3/23 ,  H03K6/04

    Abstract: @ A timebase circuit for use in the vertical timebase of a television receiver in which a linearity control current fed to the ramp capacitor is derived by multiplying a current proportional to the difference between the instantaneous and average ramp voltages by a reference current which may be adjusted to control linearity.

    VERTICAL SYNC COUNTER WITH AUTOMATIC RECOGNITION OF TV LINE STANDARD
    33.
    发明专利
    VERTICAL SYNC COUNTER WITH AUTOMATIC RECOGNITION OF TV LINE STANDARD 未知

    公开(公告)号：DE3279381D1

    公开(公告)日：1989-02-23

    申请号：DE3279381

    申请日：1982-09-17

    Applicant: MOTOROLA INC

    Inventor： NEWTON ANTHONY DAVID

    IPC: H04N5/04 ,  H04N3/27 ,  H04N5/12 ,  H04N5/46

    Abstract: A TV timebase circuit includes a vertical sync counter in the form of a ten-bit ripple-through counter. Additional logic circuitry including a pair of divide-by-four counters, a latch, a D flip-flop, and associated AND, NAND, and invertor gates are also provided. The circuit is responsive to a multiple of the horizontal frequency and to vertical sync pulses and is capable of automatic recognition of 525 or 625 line standard. The logic includes a mechanism for locking out the vertical counter's 525 count when operating in the 625 mode. The latch, in association with one of the divide-by-four counters serves a "fly wheel" sync function, whereby a predetermined number of "matches" must be recognized to lock the circuit into a given mode, and whereby a predetermined number of "mis-matches" must occur to drop the circuit operation from the locked-in mode. Several outputs are taken off the vertical counter to operate ramp drive and blanking functions of the TV vertical sweep generator. An output representative of the particular line standard being decoded may be used to provide chrominance decoding information and picture height control information. An alternative embodiment capable of recognizing any given TV line standard comprises a register which is loadable with the line standard number, which in turn is provided from the vertical counter cumulative count between successive vertical sync pulses, the vertical counter being reset by each vertical sync pulse. Comparison logic is provided for locking the counter circuit onto a given line standard after a predetermined number of successful matches have occurred between the contents of the register and the vertical counter count at the moment of reset by the vertical sync pulse.

    FAILURE DETECTION CIRCUIT
    34.
    发明专利
    FAILURE DETECTION CIRCUIT 未知

    公开(公告)号：GB2160078A

    公开(公告)日：1985-12-11

    申请号：GB8414312

    申请日：1984-06-05

    Applicant: MOTOROLA INC

    Inventor： JOBLING DAVID TREVOR ,  NEWTON ANTHONY DAVID

    IPC: H04N17/04 ,  H04N3/20

    Abstract: A television deflection system failure detection circuit is described in which a first latch (8) is set during a first portion of the frame period and is reset by a fly-back signal the output of the latch being gated by a gating circuit (17, 19-21) to set a reset or output latch (18) during a second portion of the frame period which does not overlap the first portion, and in dependence upon the state of the first latch (8).

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