公开(公告)号：JPH0576226B2

公开(公告)日：1993-10-22

申请号：JP50296082

申请日：1982-09-17

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID

IPC: H04N5/04 ,  H04N3/27 ,  H04N5/12 ,  H04N5/46

公开(公告)号：JPS58501749A

公开(公告)日：1983-10-13

申请号：JP50296082

申请日：1982-09-17

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID

IPC: H04N5/04 ,  H04N3/27 ,  H04N5/12 ,  H04N5/46

公开(公告)号：GB2330024B

公开(公告)日：2001-08-29

申请号：GB9721055

申请日：1997-10-03

Applicant: MOTOROLA INC

Inventor： STAUFER HANS ,  NEWTON ANTHONY DAVID

IPC: H04L27/06 ,  G06K7/00 ,  H03D1/18 ,  H03D1/22 ,  H03D1/24 ,  G06K19/077

Abstract: A synchronous demodulator (10) drives an output antenna (21) with a push-pull driver circuit (13). The push-pull driver circuit (13) includes two transistors connected in a push-pull configuration driving a center-tapped transformer (17). The transformer (17) couples the push-pull driver circuit (13) to an antenna (21). Received signals are demodulated in the output driver circuit (13).

公开(公告)号：GB2331643A

公开(公告)日：1999-05-26

申请号：GB9724656

申请日：1997-11-22

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID

IPC: H03L7/07 ,  H03L7/087

Abstract: A local oscillator arrangement (100) comprises a voltage controlled oscillator (1) incorporated in a phase locked loop circuit having a signal frequency input (4), a frequency locked loop circuit including a reference crystal oscillator (10) and operable to control the frequency of the voltage controlled oscillator (1) and a feedback loop (18) within the frequency locked loop circuit to adjust the reference crystal oscillator frequency and phase so as to resolve the conflict imposed on oscillator (1) to lock on to one of a transmission signal Fs received (at 4) and the crystal oscillator (9,10) output. The phase locked loop includes a wideband filter (3) to reduce the noise of the controlled oscillator and the frequency lock loop assists in pulling the oscillator (1) to lock. The output of the oscillator (1) may be suitably combined in a superheterodyne or direct conversion mixer arrangements.

公开(公告)号：GB2273812B

公开(公告)日：1997-01-08

申请号：GB9226990

申请日：1992-12-24

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID

IPC: G02B23/12 ,  H01J31/50 ,  H01J31/56

公开(公告)号：GB2273812A

公开(公告)日：1994-06-29

申请号：GB9226990

申请日：1992-12-24

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID

IPC: G02B23/12 ,  H01J31/50 ,  H01J31/56

Abstract: An image enhancement device 10 in which light emitted from a source 8 passes through a set of colour filters 21, 31, 41 and falls upon a set of photocathodes 22. Electrons emitted by the photocathodes are accelerated by an electric field before impacting a set of phosphors 23. Light generated by the phosphors then falls upon a further set of photocathodes 24. The process is then repeated until the enhanced image 9 is emitted by the final set of phosphors 27. The filters may chosen such that the first and final images have the same colour characteristic. Alternatively, if the first image is a photographic colour negative, the filters are chosen such that the final image has normal colour.

公开(公告)号：GB2160079A

公开(公告)日：1985-12-11

申请号：GB8414315

申请日：1984-06-05

Applicant: MOTOROLA INC

Inventor： JOBLING DAVID TREVOR ,  NEWTON ANTHONY DAVID

IPC: H04N3/22 ,  H04N3/223 ,  H04N5/14

Abstract: A timebase circuit is described, for compensation of picture dimensions of television type display, for EHT fluctuations in which a control current (ic) is derived by multiplying (17) a current (IEHT) dependent upon the picture beam current with a reference current (IDAC) derived from a digital to analogue converter (19) fed with a digital code.

公开(公告)号：WO1982002987A1

公开(公告)日：1982-09-02

申请号：PCT/US1982000097

申请日：1982-01-25

Applicant: MOTOROLA INC

Inventor： MOTOROLA INC ,  NEWTON ANTHONY DAVID

IPC: H03K05/26

CPC classification number: G01R17/00 ,  G01R25/00

Abstract: Un circuit detecteur de phases (10) possede de faibles decalages et peut etre fabrique facilement comme un circuit integre bipolaire. Une premiere entree (11) sur le detecteur de phases commande un transistor (14) qui a son tour commande une source de courant (17). La sortie de la source de courant est connectee a un miroir de courant qui possede un transistor NPN (22). Le miroir de courant est connecte a la terre par un transistor (27) qui est commande par un second signal d'entree (12). Lorsque le premier signal d'entree (11) est present et est dephase avec le second signal d'entree (12), la sortie du detecteur de phase circule depuis la source de courant au travers de la jonction de la base du collecteur du transistor NPN (22). Lorsque les deux signaux d'entree (11, 12) sont en phase, la sortie du detecteur de phases (10) sert de receptrice de courant dont les capacites porteuses de courant sont commandees par la sortie de la source de courant.

公开(公告)号：GB2390495A

公开(公告)日：2004-01-07

申请号：GB0215582

申请日：2002-07-05

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID ,  LEHNING HEINZ

IPC: H04B1/40 ,  H04B17/00

Abstract: The invention relates to gain calibration in a transceiver unit (100) having a transmitter unit and a receiver unit and a feed back coupling (165) between these. A signal level measurement unit (163) measures signal levels of a feedback signal through either the receiver unit or through a signal level detector (167). A reference signal level of the feedback signal is set by adjusting the transmitter until the signal level measurement unit (163) measures a predefined value when connected through the signal level detector (167). An absolute value of the transmitter gain is then calibrated. The signal level measurement unit (163) is connected through the receiver unit and the absolute gain of the receiver is calibrated. A gain is changed either in the receiver or the transmitter unit. The relative signal level change of the feedback signal is measured and used to calibrate the gain step.

公开(公告)号：HK4492A

公开(公告)日：1992-01-17

申请号：HK4492

申请日：1992-01-16

Applicant: MOTOROLA INC

Inventor： NEWTON ANTHONY DAVID

IPC: H04N5/04 ,  H04N3/27 ,  H04N5/12 ,  H04N5/46

Abstract: A TV timebase circuit includes a vertical sync counter in the form of a ten-bit ripple-through counter. Additional logic circuitry including a pair of divide-by-four counters, a latch, a D flip-flop, and associated AND, NAND, and invertor gates are also provided. The circuit is responsive to a multiple of the horizontal frequency and to vertical sync pulses and is capable of automatic recognition of 525 or 625 line standard. The logic includes a mechanism for locking out the vertical counter's 525 count when operating in the 625 mode. The latch, in association with one of the divide-by-four counters serves a "fly wheel" sync function, whereby a predetermined number of "matches" must be recognized to lock the circuit into a given mode, and whereby a predetermined number of "mis-matches" must occur to drop the circuit operation from the locked-in mode. Several outputs are taken off the vertical counter to operate ramp drive and blanking functions of the TV vertical sweep generator. An output representative of the particular line standard being decoded may be used to provide chrominance decoding information and picture height control information. An alternative embodiment capable of recognizing any given TV line standard comprises a register which is loadable with the line standard number, which in turn is provided from the vertical counter cumulative count between successive vertical sync pulses, the vertical counter being reset by each vertical sync pulse. Comparison logic is provided for locking the counter circuit onto a given line standard after a predetermined number of successful matches have occurred between the contents of the register and the vertical counter count at the moment of reset by the vertical sync pulse.