CLOCK SIGNAL GENERATING METHOD AND CLOCK GENERATOR

    公开(公告)号:JPH10308731A

    公开(公告)日:1998-11-17

    申请号:JP12176897

    申请日:1997-04-24

    Abstract: PROBLEM TO BE SOLVED: To generate a clock signal synchronized with receiving data at a high speed in a data receiver. SOLUTION: This method generates a clock signal SCLK substantially synchronized with receiving data which is used in a data receiver 6. Receiving data is provided with a synchronous word that has a prescribed frequency ftx and a prescribed value. This method generates n clocks (CLK1 to 8) which virtually has a frequency fclk of the prescribed data frequency ftx and also whose phase is deviated by 1/n clock cycle from an adjacent clock (A), uses each of n clocks, samples the synchronous word and also decides which one optimally synchronizes with the synchronous word among n clocks (B) and is also provided with each stage that offers a prescribed one among n clocks which offers the clock signal SCLK to an output 18 (C).

    TIMEBASE CIRCUIT
    3.
    发明专利

    公开(公告)号:GB2160079A

    公开(公告)日:1985-12-11

    申请号:GB8414315

    申请日:1984-06-05

    Applicant: MOTOROLA INC

    Abstract: A timebase circuit is described, for compensation of picture dimensions of television type display, for EHT fluctuations in which a control current (ic) is derived by multiplying (17) a current (IEHT) dependent upon the picture beam current with a reference current (IDAC) derived from a digital to analogue converter (19) fed with a digital code.

    TIMEBASE CIRCUIT
    4.
    发明专利

    公开(公告)号:HK22591A

    公开(公告)日:1991-04-04

    申请号:HK22591

    申请日:1991-03-26

    Applicant: MOTOROLA INC

    Abstract: @ A timebase circuit for use in the vertical timebase of a television receiver in which a linearity control current fed to the ramp capacitor is derived by multiplying a current proportional to the difference between the instantaneous and average ramp voltages by a reference current which may be adjusted to control linearity.

    FAILURE DETECTION CIRCUIT
    5.
    发明专利

    公开(公告)号:GB2160078A

    公开(公告)日:1985-12-11

    申请号:GB8414312

    申请日:1984-06-05

    Applicant: MOTOROLA INC

    Abstract: A television deflection system failure detection circuit is described in which a first latch (8) is set during a first portion of the frame period and is reset by a fly-back signal the output of the latch being gated by a gating circuit (17, 19-21) to set a reset or output latch (18) during a second portion of the frame period which does not overlap the first portion, and in dependence upon the state of the first latch (8).

    9.
    发明专利
    未知

    公开(公告)号:DE3582612D1

    公开(公告)日:1991-05-29

    申请号:DE3582612

    申请日:1985-06-03

    Applicant: MOTOROLA INC

    Abstract: A timebase circuit is described, for compensation of picture dimensions of television type display, for EHT fluctuations in which a control current (ic) is derived by multiplying (17) a current (IEHT) dependent upon the picture beam current with a reference current (IDAC) derived from a digital to analogue converter (19) fed with a digital code.

    10.
    发明专利
    未知

    公开(公告)号:DE3578543D1

    公开(公告)日:1990-08-09

    申请号:DE3578543

    申请日:1985-06-03

    Applicant: MOTOROLA INC

    Abstract: @ A timebase circuit for use in the vertical timebase of a television receiver in which a linearity control current fed to the ramp capacitor is derived by multiplying a current proportional to the difference between the instantaneous and average ramp voltages by a reference current which may be adjusted to control linearity.

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