公开(公告)号：CA2057013C

公开(公告)日：1995-01-17

申请号：CA2057013

申请日：1990-07-09

Applicant: MOTOROLA INC

Inventor： TAHERNIA OMID ,  DAVIS WALTER L ,  HEROLD BARRY W

IPC: H04B1/16 ,  H03J5/02 ,  H03L7/187 ,  H04B1/26 ,  H04Q7/14

Abstract: A paging receiver has a synthesizer for governing the receive frequency. The paging receiver further has characteristics which are varied in response to the receive frequency. These characteristics include varying the bandwidth (52) of a loop filter (26) within a phase lock loop (16) within the synthesizer as well as varying the time in which a detector circuit used to extract a DC level from a recovered audio signal is disabled. Furthermore, the bandwidth of the loop filter is varied in response to switching from a first receive frequency to a second receive frequency in order to provide for either a uniform frequency lock time (54) or for a rapid frequency lock time. Furthermore, the time in which the detector circuit is disabled is correspondingly changed.

公开(公告)号：CA1332184C

公开(公告)日：1994-09-27

申请号：CA564695

申请日：1988-04-21

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  WILLARD DAVID F ,  TAHERNIA OMID ,  PAGE JAMES C ,  SPIRO ALLAN I ,  LAMBRECHT FRANK E

IPC: H04Q7/16 ,  G08B3/10 ,  H04B1/16

Abstract: SUBSTITUTE REMPLACEMENT SECTION is not Present Cette Section est Absente

公开(公告)号：NO920428A

公开(公告)日：1992-02-03

申请号：NO920428

申请日：1992-02-03

Applicant: MOTOROLA INC

Inventor： TAHERNIA OMID ,  DAVIS WALTER LEE ,  HEROLD BARRY WAYNE

IPC: H04B20060101 ,  H04B1/06

公开(公告)号：NO912654L

公开(公告)日：1991-07-08

申请号：NO912654

申请日：1991-07-08

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY W ,  TAHERNIA OMID

IPC: H03K20060101 ,  H03K23/48

公开(公告)号：NO912654D0

公开(公告)日：1991-07-08

申请号：NO912654

申请日：1991-07-08

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY W ,  TAHERNIA OMID

IPC: H03K20060101 ,  H03K23/48 ,  H03K

公开(公告)号：DK124191A

公开(公告)日：1991-06-25

申请号：DK124191

申请日：1991-06-25

Applicant: MOTOROLA INC

Inventor： HEROLD BARRY W ,  TAHERNIA OMID

IPC: H03K23/00 ,  H03K23/64 ,  H03K23/66 ,  H03K23/48

Abstract: A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.