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    DIGITIZED STORED VOICE PAGING RECEIVER
    2.
    发明专利
    DIGITIZED STORED VOICE PAGING RECEIVER 未知

    公开(公告)号：CA1340004C

    公开(公告)日：1998-08-18

    申请号：CA616800

    申请日：1994-01-14

    Applicant: MOTOROLA INC

    Inventor： BENNETT PAUL THOMAS ,  WILLARD DAVID FRANK ,  TAHERNIA OMID ,  PAGE JAMES CLINTON ,  SPIRO ALLAN IRA ,  LAMBRECHT FRANK ELLIS

    IPC: H04W88/02 ,  H04W4/12 ,  H04Q7/18

    Abstract: A paging receiver device (10) and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory (50) of the paging receiver (10). In response to a paging user's request, the digitized stored message is recalled from memory (50), reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.

    3.
    发明专利
    未知

    公开(公告)号：DE69028113D1

    公开(公告)日：1996-09-19

    申请号：DE69028113

    申请日：1990-05-18

    Applicant: MOTOROLA INC

    Inventor： HEROLD BARRY ,  TAHERNIA OMID ,  DAVIS WALTER ,  RIVAS MARIO

    IPC: H03J5/02 ,  H03L7/18 ,  H03J1/00

    Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

    Frequency synthesizer with an interface controller and buffer memory
    4.
    发明专利
    Frequency synthesizer with an interface controller and buffer memory 未知

    公开(公告)号：HK1004583A1

    公开(公告)日：1998-11-27

    申请号：HK98102858

    申请日：1998-04-04

    Applicant: MOTOROLA INC

    Inventor： HEROLD BARRY WAYNE ,  TAHERNIA OMID ,  DAVIS WALTER LEE ,  RIVAS MARIO ALBERTO

    IPC: H03J5/02 ,  H03L7/18 ,  H03J

    Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

    7.
    发明专利
    未知

    公开(公告)号：DK124191D0

    公开(公告)日：1991-06-25

    申请号：DK124191

    申请日：1991-06-25

    Applicant: MOTOROLA INC

    Inventor： HEROLD BARRY W ,  TAHERNIA OMID

    IPC: H03K23/00 ,  H03K23/64 ,  H03K23/66 ,  H03K23/48

    Abstract: A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.

    COMMUNICATION SYSTEM FOR DYNAMIC MANAGEMENT OF A PLURALITY OF OBJECTS AND METHOD THEREFOR
    8.
    发明申请
    COMMUNICATION SYSTEM FOR DYNAMIC MANAGEMENT OF A PLURALITY OF OBJECTS AND METHOD THEREFOR 审中-公开
    一种多目标物体的动态管理通信系统及其方法

    公开(公告)号：WO2004062159A3

    公开(公告)日：2005-05-06

    申请号：PCT/US0338850

    申请日：2003-12-08

    Applicant: MOTOROLA INC

    Inventor： EATON ERIC T ,  MOCK VON ,  TAHERNIA OMID

    IPC: H04L20060101 ,  H04L12/28 ,  H04L12/56 ,  H04L29/08 ,  H04W4/02 ,  H04W4/06 ,  H04Q7/20

    CPC classification number: H04W4/02 ,  H04L67/04 ,  H04L67/18 ,  H04W4/06

    Abstract: A communication system (100) dynamically manages a plurality of objects (105). Each object (120) has a communication device (145) placed within or in close proximity to the object (120) for communicating a plurality of object information (245). A group controller (220) communicates with the communication device (145) and takes over responsibility for communication within the communication system (100) for the communication device (145) when the object location (130) comes within a communication range of the group controller (220).

    Abstract translation: 通信系统（100）动态管理多个对象（105）。 每个对象（120）具有放置在物体（120）内或紧邻对象（120）的通信设备（145），用于传送多个对象信息（245）。 当对象位置（130）进入组控制器（145）的通信范围内时，组控制器（220）与通信设备（145）通信并承担通信系统（100）内的通信责任，用于通信设备（145） （220）。

    Digitized stored voice paging receiver
    9.
    发明专利
    Digitized stored voice paging receiver 未知

    公开(公告)号：HK1005757A1

    公开(公告)日：1999-01-22

    申请号：HK98104802

    申请日：1998-06-03

    Applicant: MOTOROLA INC

    Inventor： BENNETT PAUL THOMAS ,  WILLARD DAVID FRANK ,  TAHERNIA OMID ,  PAGE JAMES CLINTON ,  SPIRO JAMES CLINTON ,  LAMBRECHT FRANK ELLIS

    IPC: H04Q7/16 ,  G08B3/10 ,  G08B

    Abstract: A paging receiver device (10) and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory (50) of the paging receiver (10). In response to a paging user's request, the digitized stored message is recalled from memory (50), reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.

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