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公开(公告)号：US11688479B2
公开(公告)日：2023-06-27
申请号：US17453289
申请日：2021-11-02
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, Jr. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
CPC classification number: G11C16/3495 , G11C16/14 , G11C16/26 , G11C16/32
Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
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公开(公告)号：US11663104B2
公开(公告)日：2023-05-30
申请号：US17691957
申请日：2022-03-10
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil, Jr. , Niccolo′ Righetti , Kishore K. Muchherla , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
CPC classification number: G06F11/3058 , G06F1/30 , G06F11/076 , G06F11/0772 , G06F11/0787 , G06F11/3037 , G11C5/141 , G11C16/3404 , G11C16/3418 , G06F2201/84
Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.
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公开(公告)号：US11556267B2
公开(公告)日：2023-01-17
申请号：US17006978
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo′ Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.
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公开(公告)号：US11487436B2
公开(公告)日：2022-11-01
申请号：US16995083
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil, Jr. , Niccolo' Righetti , Kishore K. Muchherla , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.
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公开(公告)号：US20220334756A1
公开(公告)日：2022-10-20
申请号：US17235216
申请日：2021-04-20
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Ashutosh Malshe , Giuseppina Puzzilli , Saeed Sharifi Tehrani
IPC: G06F3/06
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.
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Patent Agency Ranking
公开(公告)号：US11443812B2
公开(公告)日：2022-09-13
申请号：US17127358
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Scott A. Stoller , Pitamber Shukla , Priya Venkataraman , Giuseppina Puzzilli , Niccolo′ Righetti
Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.
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公开(公告)号：US11437111B2
公开(公告)日：2022-09-06
申请号：US17122758
申请日：2020-12-15
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil, Jr. , Karl D. Schuh , Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Kishore K. Muchherla , Gil Golov , Todd A. Marquart , Jiangang Wu , Niccolo' Righetti , Ashutosh Malshe
Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.
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公开(公告)号：US11309052B2
公开(公告)日：2022-04-19
申请号：US17001723
申请日：2020-08-25
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
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公开(公告)号：US20220068426A1
公开(公告)日：2022-03-03
申请号：US17001723
申请日：2020-08-25
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
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公开(公告)号：US20220066642A1
公开(公告)日：2022-03-03
申请号：US17006978
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.
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