公开(公告)号：AT525802T

公开(公告)日：2011-10-15

申请号：AT06789089

申请日：2006-07-31

Applicant: QUALCOMM INC

Inventor： KIM NAMSOO ,  BARNETT KENNETH CHARLES ,  APARIN VLADIMIR

IPC: H03F1/32 ,  H03F1/22

Abstract: An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.

公开(公告)号：AT462223T

公开(公告)日：2010-04-15

申请号：AT02764213

申请日：2002-04-17

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03F1/30 ,  H03F1/32 ,  H03F1/00

Abstract: The present invention provides a technique for selective cancellation of the 2nd-order or 3rd-order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors that force the DC signal to be zero. One of the bias voltages is applied to the main transistor resulting in cancellation of its selected nonlinearity. The system may be readily implemented using the integrated circuit technology such that the transistors of the bias circuit are closely matched to each other and to the main transistor. The distortion cancellation effect provided by the present invention exhibits low sensitivity to variations in the transistor processing and operational temperature.

公开(公告)号：AT432553T

公开(公告)日：2009-06-15

申请号：AT01993212

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR ,  SHAH PETER

IPC: H03F1/30 ,  H03F1/32 ,  H03F1/34 ,  H03F3/19

Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor. In accordance with the inventive teachings, the buffer has a low gain and high output impedance at first frequency (f1) of a first signal applied to the circuit and a second frequency (f2) of a second signal applied to the circuit and a unity gain and low output impedance a difference between the first and second frequencies. In another specific embodiment, the inductor is inserted between the output of the unity gain buffer and the input terminal of the transistor. In alternative embodiments, circuitry is shown for providing a direct current offset at the input of the transistor. As another alternative, the linearization circuit consists of series inductor and capacitor connected between the common and input terminals of the transistor. In yet another embodiment, the linearization circuit consists of the first and the second series inductor and capacitor circuits. The first series LC circuit is connected between the common terminal of the transistor and ground and the second series LC circuit is connected between the input terminal of the transistor and ground.

公开(公告)号：CA2680521A1

公开(公告)日：2008-10-02

申请号：CA2680521

申请日：2008-03-25

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H04B1/52

Abstract: This disclosure describes techniques for reducing adverse effects of tran smit signal leakage in a full-duplex, wireless communication system. The dis closure describes techniques for reducing adverse effects of second order di stortion and cross-modulation distortion of transmit signal leakage from a t ransmitter via a duplexer. The techniques may be effective in rejecting at l east a portion of a transmit leakage signal, thereby reducing or eliminating distortion. The adaptive filter may include an estimator circuit that gener ates a transmit leakage signal estimate. A summer subtracts the estimate fro m the received signal to cancel transmit leakage and produce an output signa l. The estimator circuit generates the transmit leakage signal estimate base d on a reference signal and feedback from the output signal. The reference s ignal approximates the carrier signal used to generate the transmit signal i n the transmitter. The reference signal may be provided by the same oscillat or used to produce the transmit carrier signal.

公开(公告)号：DE60014032T2

公开(公告)日：2005-10-06

申请号：DE60014032

申请日：2000-01-13

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03H7/42 ,  H03F3/45 ,  H03H11/32

Abstract: Many applications require the conversion of a differential current signal into a single-ended signal. The shortcomings encountered with existing approaches include poor conversion efficiency, limited bandwidth, and large size. The converter disclosed uses active devices to obtain a unit of small size and high efficiency having a wide bandwidth of operation.

公开(公告)号：CA2444700A1

公开(公告)日：2002-10-31

申请号：CA2444700

申请日：2002-04-17

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03F1/30 ,  H03F1/00 ,  H03F1/32 ,  H03F1/08 ,  H03F3/04

Abstract: The present invention provides a technique for selective cancellation of the 2nd order or 3rd order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function i s such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors that force the DC signal to be zero. One of the bias voltages is applied to the main transistor resulting in cancellatio n of its selected nonlinearity. The system may be readily implemented using th e integrated circuit technology such that the transistors of the bias circuit are closely matched to each other and to the main transistor. The distortion cancellation effect provided by the present invention exhibits low sensitivi ty to variations in the transistor processing and operational temperature.

公开(公告)号：AU1187802A

公开(公告)日：2002-04-15

申请号：AU1187802

申请日：2001-10-06

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H02H9/04

Abstract: An arrangement for protecting an element from electro-static discharge. A switch is provided to inhibit the flow of energy through the element in response to the control signal. In the illustrative embodiment, the switch is a transistor switch. A resistor is disposed between an input terminal of the transistor and the positive supply to keep the transistor on during normal operation. A capacitor is disposed between the input terminal of the transistor and ground to prevent the input voltage of the transistor from fast changing. The RC time constant is chosen to be much larger than the time constant of the ESD pulse. Consequently, input voltage of the transistor will remain unchanged near ØV and the transistor will remain off during ESD event preventing the element from conducting the discharge current and providing ESD protection.

公开(公告)号：NO20013482D0

公开(公告)日：2001-07-13

申请号：NO20013482

申请日：2001-07-13

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03H7/42 ,  H03F3/45 ,  H03H11/32 ,  H03F

Abstract: Many applications require the conversion of a differential current signal into a single-ended signal. The shortcomings encountered with existing approaches include poor conversion efficiency, limited bandwidth, and large size. The converter disclosed uses active devices to obtain a unit of small size and high efficiency having a wide bandwidth of operation.

公开(公告)号：WO02056647A2

公开(公告)日：2002-07-18

申请号：PCT/US0146190

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR ,  SHAH PETER J

IPC: H03F1/32 ,  H03F1/34 ,  H03F3/19 ,  H05F3/00

CPC classification number: H03F1/32 ,  H03F1/34 ,  H03F3/19

Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor. In accordance with the inventive teachings, the buffer has a low gain and high output impedance at first frequency (f1) of a first signal applied to the circuit and a second frequency (f2) of a second signal applied to the circuit and a unity gain and low output impedance a difference between the first and second frequencies. In another specific embodiment, the inductor is inserted between the output of the unity gain buffer and the input terminal of the transistor. In alternative embodiments, circuitry is shown for providing a direct current offset at the input of the transistor. As another alternative, the linearization circuit consists of series inductor and capacitor connected between the common and input terminals of the transistor. In yet another embodiment, the linearization circuit consists of the first and the second series inductor and capacitor circuits. The first series LC circuit is connected between the common terminal of the transistor and ground and the second series LC circuit is connected between the input terminal of the transistor and ground.

Abstract translation: 具有改善线性度和最小三阶失真的射频放大器。 放大器包括具有第一，第二和第三端子的第一晶体管，第一端子是输入端子，第二端子是输出端子，第三端子是公共端子。 包括具有第一和第二端子的线性化电路。 第一端子连接到晶体管的公共端子，第二端子连接到晶体管的输入端子。 在具体实施例中，线性化电路被实现为具有连接到晶体管的公共端子的输入端子和连接到晶体管的输入端子的输出端子的单位增益缓冲器。 根据本发明，缓冲器在施加到电路的第一信号的第一频率（f1）处施加低增益和高输出阻抗，以及施加到电路的第二信号的第二频率（f2）和单位增益 并且低输出阻抗是第一和第二频率之间的差。 在另一个具体实施例中，电感器插入在单位增益缓冲器的输出端和晶体管的输入端子之间。 在替代实施例中，示出了用于在晶体管的输入处提供直流偏移的电路。 作为另一种选择，线性化电路由连接在晶体管的公共端和输入端之间的串联电感和电容组成。 在另一个实施例中，线性化电路由第一和第二串联电感器和电容器电路组成。 第一串联LC电路连接在晶体管的公共端和地之间，第二串联LC电路连接在晶体管的输入端和地之间。

公开(公告)号：CA2839279A1

公开(公告)日：2012-12-27

申请号：CA2839279

申请日：2012-06-21

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: G06N3/08

Abstract: Certain aspects of the present disclosure support a local competitive learning rule applied in a computational network that leads to sparse connectivity among processing units of the network. The present disclosure provides a modification to the Oja learning rule, modifying the constraint on the sum of squared weights in the Oja rule. This constraining can be intrinsic and local as opposed to the commonly used multiplicative and subtractive normalizations, which are explicit and require the knowledge of all input weights of a processing unit to update each one of them individually. The presented rule provides convergence to a weight vector that is sparser (i.e., has more zero elements) than the weight vector learned by the original Oja rule. Such sparse connectivity can lead to a higher selectivity of processing units to specific features, and it may require less memory to store the network configuration and less energy to operate it.