公开(公告)号：IT8922104A1

公开(公告)日：1991-04-24

申请号：IT2210489

申请日：1989-10-24

Applicant: SGS THOMSON MICROELECTRONICS S R L

Inventor： PALARA SERGIO ,  PAPARO MARIO ,  PELLICANO' ROBERTO

IPC: G05F1/56 ,  G05F1/10 ,  G05F3/22 ,  H02H20060101 ,  H01F7/18 ,  H01L20060101 ,  H03K17/16 ,  H03K17/615

公开(公告)号：IT9022577D0

公开(公告)日：1990-12-31

申请号：IT2257790

申请日：1990-12-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PUZZOLO SANTO ,  ZAMBRANO RAFFAELE ,  PAPARO MARIO

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

公开(公告)号：IT8922104D0

公开(公告)日：1989-10-24

申请号：IT2210489

申请日：1989-10-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PALARA SERGIO ,  PAPARO MARIO ,  PELLICANO' ROBERTO

IPC: G05F1/56 ,  G05F3/22 ,  G05F1/10 ,  H01F7/18 ,  H03K17/16 ,  H03K17/615 ,  H02H ,  H01L

Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

公开(公告)号：IT8919570D0

公开(公告)日：1989-02-27

申请号：IT1957089

申请日：1989-02-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PALARA SERGIO

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K5/02

Abstract: The monolithic integrated structure comprises a semiconductor substrate (1), a superimposed first epitaxial stratum (2) having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second insulation pocket (3, 4) which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum (2) at a distance such as to define an interposed area (25) of said first stratum (2) capable of insulating said insulating pockets (3, 4) from one another. Within the latter pockets (3, 4), there are provided respective embedded strata (6, 7) and superimposed regions (8, 9) of a second epitaxial stratum having characterstics such as to withstand the low voltage applied across the two driving stages. A further region (5) of said second epitaxial stratum is superimposed over said area (25) of said first epitaxial stratum (2). The above regions (8, 9) of insulation pockets (3, 4) are designed for the formation of two high and low voltage driving stages (DR1, DR2), while the above further region (5) of the second epitaxial stratum may be used for the formation of a level translator circuit component (T3). Means (20, 21; 22, 23) are provided for the protection of said circuit component (T3) against high supply voltages.