VERTICAL STRUCTURE INTEGRATED BIPOLAR TRANSISTOR

    公开(公告)号:JPH1070133A

    公开(公告)日:1998-03-10

    申请号:JP14034497

    申请日:1997-05-29

    Inventor: PALARA SERGIO

    Abstract: PROBLEM TO BE SOLVED: To make it possible to incorporate a current sensitive resistor by suppressing the increase in total area occupied by a transistor by a method wherein a buried emitter layer is connected to the first surface emitter contact part, and a surface emitter region is brought into contact with the second surface emitter contact point along the circumferential side part of the surface emitter region. SOLUTION: N type vertical diffusion region 6 is formed in such a manner that it comes in contact with a buried emitter 5 and the emitter is guided to the surface, and buried emitter 5 is connected to a surface region 7 of the same conductivity type. A contact point 10 is formed on the edge of the surface region 7, and an emitter current is taken out from the contact point 10 through a metallization wire 12. An N type region 8 is guided to the edge of the buried emitter region 5, and it comes in contact with a contact point 11 and a metallization wire 13. The current of a transistor is allowed to flow to the buried emitter 5 from a substrate 1. through a base 3, passing through the region 6 on a resistance path R1, reaches the surface region 7, and flows to two resistance paths R2 contained between the region 6 and the emitter contact point 10.

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    发明专利
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    公开(公告)号:DE69032552T2

    公开(公告)日:1999-02-25

    申请号:DE69032552

    申请日:1990-10-18

    Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

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    发明专利
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    公开(公告)号:DE69025278D1

    公开(公告)日:1996-03-21

    申请号:DE69025278

    申请日:1990-11-22

    Abstract: The detection circuit of the current in an MOS type power transistor comprises a detection transistor (T2) connected with drain and gate in common to the power transistor (T1) and having characteristics such that the current (I2) flowing through it is equal to a fraction of the current (I1) flowing through power transistor (T1). Downstream from detection transistor (T2) there are arranged means (T6; T13) for comparing a first current (I3) equal to a fraction of the current (I2) flowing through detection transistor (T2) with a second reference current (Ig1) having a pre-set value and to produce a detection signal of the value of the current in power transistor (T1) in relation to the difference between said first current (I3) and the reference current (Ig1).

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    发明专利
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    公开(公告)号:DE69022262D1

    公开(公告)日:1995-10-19

    申请号:DE69022262

    申请日:1990-02-12

    Abstract: The monolithic integrated structure comprises a semiconductor substrate (1), a superimposed first epitaxial stratum (2) having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second insulation pocket (3, 4) which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum (2) at a distance such as to define an interposed area (25) of said first stratum (2) capable of insulating said insulating pockets (3, 4) from one another. Within the latter pockets (3, 4), there are provided respective embedded strata (6, 7) and superimposed regions (8, 9) of a second epitaxial stratum having characterstics such as to withstand the low voltage applied across the two driving stages. A further region (5) of said second epitaxial stratum is superimposed over said area (25) of said first epitaxial stratum (2). The above regions (8, 9) of insulation pockets (3, 4) are designed for the formation of two high and low voltage driving stages (DR1, DR2), while the above further region (5) of the second epitaxial stratum may be used for the formation of a level translator circuit component (T3). Means (20, 21; 22, 23) are provided for the protection of said circuit component (T3) against high supply voltages.

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    发明专利
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    公开(公告)号:DE69020100D1

    公开(公告)日:1995-07-20

    申请号:DE69020100

    申请日:1990-10-20

    Abstract: The circuit switches the power supply of the integrated circuit over to the input voltage of the switching regulator during the initial starting phase, and over to the output of said regulator once the steady state has been reached.

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    发明专利
    未知

    公开(公告)号:DE68917881D1

    公开(公告)日:1994-10-06

    申请号:DE68917881

    申请日:1989-12-04

    Abstract: The generator of drive signals comprises a ramp generator (11) suitable for receiving a square waveform input signal and for converting it into an output signal variable between a lower level and an upper level with upward and downward ramps having a preset slope, a first comparator (21) with a non-inverting input connected to the output of said ramp generator (11) and an inverting input connected to a first reference signal source (23) and a second comparator (22) with an inverting input connected to the output of said ramp generator (11) and a non-inverting input connected to a second reference signal source (24).

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    发明专利
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    公开(公告)号:IT1236667B

    公开(公告)日:1993-03-25

    申请号:IT2228989

    申请日:1989-11-07

    Abstract: The device accomplishes the protection against breakdown of an N+ type diffuse region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxlal layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffuse region (6). The diffuse region (6) is insulated electrically with respect to the A type containment region (5).

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    发明专利
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    公开(公告)号:IT1231541B

    公开(公告)日:1991-12-17

    申请号:IT2129589

    申请日:1989-07-25

    Abstract: The device for protection against the parasitic effects caused by negative impulses of power supply voltages is applied to monolithic integrated circuits including a power device (Q3, Q4) for driving an inductive load (L) and a control device (R3, R2, Q2, Q5) with a voltage limiter (Q2, Z1) for the power device (Q3, Q4). It provides for the introduction of shielding elements (40, 70) accomplished in the form of annular pockets, of various sizes, suitable for the containment of the voltage limiter's active components.

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    发明专利
    未知

    公开(公告)号:IT1230326B

    公开(公告)日:1991-10-18

    申请号:IT2115089

    申请日:1989-07-11

    Inventor: PALARA SERGIO

    Abstract: To a power device (T1, T2; T11) with related control circuit (A1, T3), both of the semiconductor type in the form of an integrated circuit, there is associated a protection circuit which comprises a switch (T6) sensitive to negative overvoltages across the power supply and suitable for enabling a limiter (T4, Z1; T14) of the voltage applied across the power device (T1, T2; T11).

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