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公开(公告)号：JPH10285611A
公开(公告)日：1998-10-23
申请号：JP8129297
申请日：1997-03-31
Applicant: SONY CORP
Inventor： OKUDA TAKUSHI , KUROKAWA MASUYOSHI , IWASE SEIICHIRO
Abstract: PROBLEM TO BE SOLVED: To easily set the contents of a chroma key processing by a GUI (graphic user interface) operation. SOLUTION: A personal computer 72 displays GUI images for setting a background color at a monitor for the computer. A user specifies the range of the color desired to be turned to the background color by the mouse or the like of an input device 70 for the display of a color space for which the chroma signals Cb and Cr of the GUI images for setting the background color are a y axis and an x axis. The personal computer 72 turns the entire specified range to the background color (key color), generates a program for superimposing a background image to the part of the background color of a foreground image so as to be fitted and down-loads it to a DSP(digital signal processor) 80. The DSP 80 executes the down-loaded program, performs the chroma key processing and displays the result of the processing on the monitor 76.
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公开(公告)号：JPH0877002A
公开(公告)日：1996-03-22
申请号：JP20780594
申请日：1994-08-31
Applicant: SONY CORP
Inventor： OKI MITSUHARU , YAMAZAKI TAKAO , KUROKAWA MASUYOSHI , HASHIGUCHI AKIHIKO
Abstract: PURPOSE: To provide the parallel processor device which performs efficient arithmetic processing according to signals that are different in data length. CONSTITUTION: A parallel processor 1 is constituted by connecting a 1st processor 10 and a 2nd processor having (n) unit processors 1001 and (m-n) unit processors 200p in series. For signals of =(n) data as units of processing, those parallel processor devices are connected and used as one parallel processor device and the same arithmetic processing with a conventional parallel processor device is performed. For signals whose data length is
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公开(公告)号：JPH07312558A
公开(公告)日：1995-11-28
申请号：JP10513994
申请日：1994-05-19
Applicant: SONY CORP
Inventor： OKI MITSUHARU , HASHIGUCHI AKIHIKO , FURUNO KATSUNAO , KUROKAWA MASUYOSHI , YAMAZAKI TAKAO , IWASE SEIICHIRO
Abstract: PURPOSE:To prevent overwrite with simple circuit configuration by connecting a 1st serial parallel S/P conversion circuit and a 3rd S/P conversion circuit or a 2nd S/P conversion circuit and the 3rd conversion circuit differentially, receiving data of a group serially and outputting the data in parallel. CONSTITUTION:When switches UiA (i=1-3) of a 1st group and switches Uj (j=4-9) of a 3rd group are sequentially closed by a 1st read pointer, data being components of input data IN are latched sequentially in registers RiA and Rj. Similarly the data are sequentially delayed by 1st bit unit time delay elements H1B-H3B of a 2nd group and delayed by 1st bit unit time delay elements H4-H9 by a 2nd write pointer WPB. A 1st read enable signal REA and a 2nd signal REB are applied alternately in an alternate timing. Then the signal REA or REB is applied to a switch Tj via an OR circuit ORR, then data latched in the registers R4-R9 are outputted from an output terminal OUT.
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公开(公告)号：JPH07146781A
公开(公告)日：1995-06-06
申请号：JP31450893
申请日：1993-11-19
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PURPOSE:To reduce the number of steps required for a multiplication calculation and to realize the improvement of processing speed by applying the algorithm of a booth to the decoding means of a unit signal processing part in which a 1-bit full adder is incorporated. CONSTITUTION:A processor 1 is constituted by parallel connecting signal processing stages 2 in plural stages. Each of the signal processing stages 2 has a shift register 3 for data input, a shift register 4 for data output and a storage means 5 which is used for the storage of data and an arithmetic processing, and is provided with a unit signal processing part 6 in which a decoding means decoding data and a 1-bit full adder are incorporated based on a booth algorithm. Namely, by applying the algorithm of the booth to the decoding means of the unit signal processing part 6 in which the 1-bit full adder is incorporated, the number of times of addition of a multiplicand can be reduced by half and the number of steps which is necessary for the unit signal processing part 6 to perform a multiplication calculation can be reduced.
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公开(公告)号：JPH03249790A
公开(公告)日：1991-11-07
申请号：JP4864090
申请日：1990-02-28
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PURPOSE:To simultaneously read out several nibbles by providing a multiplexer which is connected to an input register for holding input data and outputs the input data at every prescribed unit instructed by a control code. CONSTITUTION:Input data 1 read out in parallel from an image memory are held in an input register 6. A multiplexer 7 executes a parallel-serial conversion, and also, changes the sequence of an output in accordance with a write side of an image memory. The sequence outputted from the multiplexer 7 is designated by a control code from a counter. As for the counter, loading from a host computer can be executed, and the control of the sequence of the output executed by the multiplexer 7 can be set to a desired one. In such a way, by changing a value loaded to the counter for generating the control code, various nibble swapping can be executed.
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Patent Agency Ranking36.发明专利
公开(公告)号：JP2013142775A
公开(公告)日：2013-07-22
申请号：JP2012002903
申请日：2012-01-11
Inventor： YAMASHITA JUNICHI , UCHINO KATSUHIDE , UCHIDA TAKASHI , SENOO YUKI , UEDA KAZUHIKO , KUROKAWA MASUYOSHI
CPC classification number: G09G5/02 , G09G3/20 , G09G3/32 , G09G2320/0271 , G09G2320/0285 , G09G2320/046
Abstract: PROBLEM TO BE SOLVED: To correct deterioration due to ghosting.SOLUTION: There is provided a display device including: a sampling unit sampling image data continuously inputted thereto at predetermined intervals; a gradation value/deterioration amount converting unit converting a gradation value of an image based on the image data sampled in the sampling unit into a deterioration amount; a deterioration amount storing unit calculating and accumulating a difference in deterioration amount between a correction object pixel and a reference pixel by using the deterioration amount obtained through the conversion in the gradation value/deterioration amount converting unit; a correction amount calculating unit calculating a correction amount required for resolving the difference in deterioration amount stored in the deterioration amount storing unit on the basis of an estimated deterioration amount within a correction period of time; and a deterioration amount difference correcting unit correcting the gradation value of a corresponding pixel with the correction amount thus calculated. This technique can be applied to a display comprising a self-luminous element.
Abstract translation: 要解决的问题：纠正由于重影引起的劣化。解决方案：提供一种显示装置，包括：采样单元，以预定间隔对连续输入的图像数据进行采样; 灰度值/劣化量转换单元，将基于在采样单元中采样的图像数据的图像的灰度值转换为劣化量; 劣化量存储单元通过使用通过灰度值/劣化量转换单元中的转换获得的劣化量来计算和累积校正对象像素和参考像素之间的劣化量差异; 校正量计算单元，基于校正时间段内的估计劣化量，计算解决存储在劣化量存储单元中的劣化量差异所需的校正量; 以及劣化量差校正单元，用这样计算的校正量对相应像素的灰度值进行校正。 该技术可以应用于包括自发光元件的显示器。
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公开(公告)号：JP2009077382A
公开(公告)日：2009-04-09
申请号：JP2008186098
申请日：2008-07-17
Inventor： IHARA TOSHINORI , OKADA SHINTARO , NISHI TOMOHIRO , NISHIBORI KAZUHIKO , KUROKAWA MASUYOSHI
IPC: H04N7/01
Abstract: PROBLEM TO BE SOLVED: To suppress the breakdown of a generated interpolated image even in an image having a large brightness change which may be easily broken down in motion compensation processing using a motion vector in generating an interpolated image. SOLUTION: A sum-of-absolute-differences calculation unit 12a calculates a sum of absolute differences between corresponding pixels in a notice block of a notice pixel in an input image and in a reference block of a reference pixel in a just preceding image. A comparison unit 12b compares the sums of absolute differences to find out a minimum sum of absolute differences. A motion vector calculation part 12c extracts a motion vector of the notice pixel on the basis of the reference pixel having the minimum sum of absolute differences and the notice image. A motion compensation processing unit 13 generates an MC image by adopting the pixel values of respective pixels in the input image as the pixel values of pixels in the MC image on the basis of the motion vector. An accumulation unit 14a cumulatively adds sums of absolute differences in the input image which correspond to respective pixels in the MC image. A synthesis unit 14c synthesizes respective pixels in the input image and respective pixels in the corresponding MC image on the basis of the cumulative addition result to generate an interpolated image. COPYRIGHT: (C)2009,JPO&INPIT
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公开(公告)号：JP2007020022A
公开(公告)日：2007-01-25
申请号：JP2005201107
申请日：2005-07-11
Inventor： NISHI TORU , ASANO MITSUYASU , UEDA KAZUHIKO , KUROKAWA MASUYOSHI , NISHIBORI KAZUHIKO
CPC classification number: H04N7/0137 , G09G3/20 , G09G2310/0221 , G09G2320/103 , G09G2340/0435 , G09G2340/16 , G09G2360/18 , H04N7/0127
Abstract: PROBLEM TO BE SOLVED: To display a video signal with high image quality according to various characteristics of a display device by applying a video signal processor and a video signal processing method, for example, to the generation of the driving signal for a liquid crystal display panel.
SOLUTION: In this processor, output video signals S21, S22 of a plurality of systems are outputted by dividing an input video signal S1 into the plurality of systems so that the input video signal S1 becomes not over clock frequency, which can be processed by a display part 12, according to the display part 12, and the respective areas AR1, AR2 formed by dividing a displayable area of the display part 12 are driven by the output video signals S21, S22, respectively.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：通过应用视频信号处理器和视频信号处理方法，根据显示装置的各种特性来显示具有高图像质量的视频信号，例如，产生用于 液晶显示面板。 解决方案：在该处理器中，通过将输入视频信号S1分割成多个系统来输出多个系统的输出视频信号S21，S22，使得输入视频信号S1变得不超过时钟频率，其可以是 根据显示部分12由显示部分12处理，并且分别由显示部分12的可显示区域形成的各个区域AR1，AR2分别由输出视频信号S21，S22驱动。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JPH10285430A
公开(公告)日：1998-10-23
申请号：JP8129497
申请日：1997-03-31
Applicant: SONY CORP
Inventor： OKUDA TAKUSHI , KUROKAWA MASUYOSHI , KONDO YOSHITO , IWASE SEIICHIRO
IPC: H04N5/14 , G06F17/50 , G06T1/20 , G06T5/20 , H03H17/02 , H03H17/08 , H04N1/40 , H04N1/409 , H04N5/208 , H04N5/21
Abstract: PROBLEM TO BE SOLVED: To simplify the operation from the decision of a filter specification until its evaluation by using a GUI. SOLUTION: A user sets a filtering characteristics (frequency response) based on a GUI menu for setting the characteristic in S380. A computer generates a filter coefficient to realize the filtering characteristic in S382. The computer uses the filter characteristic to design an FIR filter in S384. The computer generates a program for a DSP to realize the designed FIR filter in S386. The computer downloads to the DSP in S388, and the DSP executes the program to apply filtering processing to image data. The computer describes the designed filter circuit by a hardware description language and provides an output.
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公开(公告)号：JPH10134176A
公开(公告)日：1998-05-22
申请号：JP28710396
申请日：1996-10-29
Applicant: SONY CORP
Inventor： NAKAMURA KENICHIRO , KUROKAWA MASUYOSHI , KANO MAMORU , AOYAMA KOJI
Abstract: PROBLEM TO BE SOLVED: To easily vary the number of taps and a conversion ratio in a short time by automatically setting a filter program and a filter coefficient according to filter specification information and performing filter operation. SOLUTION: Pixel data of one horizontal line after being inputted to an input register 24 in order from an image input terminal 10 are supplied to an upper processor element(PE) group 21 in parallel. The PE group 21 performs filter operation processing for respective pixel data that respective element processors 23 have received by using a control instruction from a controller 26 and coefficient data from a coefficient memory 27. The processing result of the upper PE group 21 is inputted to the lower PE group 22 as it is in parallel and filter operation processing is further performed when necessary. The processing result of the PE group 22 is inputted to an output register 25 in parallel and outputted, pixel by pixel, in order. The processing like this is repeated as many times as vertical lines to perform two-dimensional image processing.
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