公开(公告)号：JPH08129857A

公开(公告)日：1996-05-21

申请号：JP28857394

申请日：1994-10-31

Applicant: SONY CORP

Inventor： MATSUMOTO YOSHIO ,  FUKUSHIMA TAKASHI ,  OGA NORIO

IPC: G11B20/12 ,  G11B27/00 ,  G11B27/034 ,  G11B27/10

Abstract: PURPOSE: To easily access to a specified track during reproducing by giving priority to an optional track as an important track and discriminating this track from a usual track. CONSTITUTION: When a track to be accessed is determined by means of an AMS access direction and an important track number read in S-RAM 11a, the number of this track is set as a reproducing track number TNOPp. Accessing is performed by determining the start address of the reproducing track number TNOp from a UTOC sector 0 and when track program searching accessing is finshed, in step F204, reproducing is started from its location.

公开(公告)号：JPH07169184A

公开(公告)日：1995-07-04

申请号：JP34195093

申请日：1993-12-13

Applicant: SONY CORP

Inventor： MATSUMOTO YOSHIO ,  NAKA HIDEO

IPC: G11B15/10 ,  G11B19/02 ,  G11B20/00 ,  G11B20/04

Abstract: PURPOSE:To attain the cost reduction by omitting an automatic/manual changeover switch and a recording volume key. CONSTITUTION:When a recording key is kept depressing for a prescribed time in a recording pose state in which the recording key and the pose key of an operation part 20 are depressed, this recorder is changed over from an AGC circuit 13 to an amplifier circuit 11 and further the fast-forwarding key and the fast-rewinding key become a recording level setting key. By this, the manual setting of a recording level is made possible. Thus, the cost can be reduced because the automatic/manual changeover switch and the recording volume key can be omitted.

公开(公告)号：JPH04285748A

公开(公告)日：1992-10-09

申请号：JP7202991

申请日：1991-03-13

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  MATSUMOTO YOSHIO ,  KAN TOSHIYA

IPC: G11B15/467

Abstract: PURPOSE:To record data by making a rotary drum system and a recording signal process system to an asynchronous state. CONSTITUTION:Though a phase synchronization is not made for a driving motor 35 of the rotary drum and the signal processing systems 14, 15, 16 and 17, the recorded data are transmitted to rotary heads 19A, 19B at a prescribed timing through a SIO bus 30 by providing a programable timing signal generator 33.

公开(公告)号：JPH04247305A

公开(公告)日：1992-09-03

申请号：JP3207591

申请日：1991-01-31

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  MATSUMOTO YOSHIO

IPC: G11B5/027

Abstract: PURPOSE:To additionally improve the hand of use by simplifying an operation for switching circuits to an input source selected by a user. CONSTITUTION:The connection of an adapter having a 2nd input means provided separately to the body of the recorder having a 1st input means on the body side of the recorder to the body of this recorder is detected by the detecting means on the body side of the recorder when this adapter is connected to the body of the recorder. The body of the recorder is then controlled to be switched to the 2nd input means side provided on the adapter side.

公开(公告)号：JPH04168363A

公开(公告)日：1992-06-16

申请号：JP29409690

申请日：1990-10-31

Applicant: SONY CORP

Inventor： MATSUMOTO YOSHIO ,  TANAKA MASATO

IPC: G01P3/486 ,  G11B15/093

Abstract: PURPOSE:To make it possible to decrease power consumption futhermore by computing the stopping time of light emission of a light emitting part in the second period based on the first period of a detected rotation signal. CONSTITUTION:A reflecting plate 4 is provided on a specified rotating part 3 so that the parts having the different reflectivities are alternately formed. The light from a light emitting part 5 is reflected from the reflecting plate 4. The reflected light is received with a light receiving part 6. Thus, a detected rotation signal S6 whose periods T1 - T3 are changed in response to the rotating speed of the rotating part 3 is obtained. A masking time T1 of the second period T2 of the signal S6 is computed based on the first period T1 of the signal S6. The light emission of the light emitting part 5 is stopped for the specified time T1 in the second period T2 based on the result of the computation. In this way, the light emitting part 5 emits the light only when the signal S6 rises up. The rising edge of the signal S6 which is used for detecting the rotation is positively obtained. The light emission of the light emitting part 5 can be stopped at the period other than the rising time.

公开(公告)号：JPH01286064A

公开(公告)日：1989-11-17

申请号：JP11625888

申请日：1988-05-13

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  MATSUMOTO YOSHIO

IPC: G06F13/14

Abstract: PURPOSE:To enhance data transmitting efficiency by sending an address automatic setting information, and then continuously transmitting original data. CONSTITUTION:The data from a CPU 10 are serially transmitted through a serial interface circuit 10 to plural devices 11, 12, 13.... At the time of the transmission, by sending the address data after the sending of an address setting instruction, an address is set, and the data corresponding to the set address are transmitted. The address automatic setting instruction to automatically switching-control the set contents of the address is provided, and by this address automatic setting instruction, after the high-order, low-order, etc., of the address to be set are automatically switching-controlled, the address data and the data to be processed are continuously transmitted from the CPU 10.

公开(公告)号：JPH01286063A

公开(公告)日：1989-11-17

申请号：JP11625588

申请日：1988-05-13

Applicant: SONY CORP

Inventor： HIMENO TAKUJI ,  MATSUMOTO YOSHIO

IPC: G06F13/14 ,  H04L12/40

Abstract: PURPOSE:To enhance data transmitting efficiency between a processor and a prescribed device by including the bank designating information of an address in an address setting instruction. CONSTITUTION:Data from a CPU 10 are serially transmitted through a serial interface circuit 20 to plural devices 11, 12, 13.... At the time of a transmission, after the sending of an address setting instruction, by sending the address data, the address is set, and the data corresponding to the set address are transmitted. The information to designate the plural banks are included in the address setting instruction, and by the address setting instruction attached with the bank designating information and the address data to be next sent, the address in the designated bank is designated.

公开(公告)号：JPS6453646A

公开(公告)日：1989-03-01

申请号：JP11625788

申请日：1988-05-13

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  MATSUMOTO YOSHIO

IPC: H04L12/40

Abstract: PURPOSE:To send the same instruction to many devices at high speed by providing a means to update a device address based on serially transmitted code data. CONSTITUTION:When a series of data corresponding to a continuous address is transmitted from a CPU 10 side to a device 11, first, 8 bits of a peak address are transmitted. The address is fetched into an address counter 33 in the device 11, the function of the adjustment of the sound recording volume of a left channel is selected by the address value. Next, when the volume value data are transmitted, they are fetched into a data buffer 34 and the volume adjustment is executed. Next, when the command is sent, an address changing control circuit 37 becomes the action condition and each time the control data value is transmitted, the counter 33 is incremented one by one, and the device address is updated.

公开(公告)号：JPS63281545A

公开(公告)日：1988-11-18

申请号：JP11754287

申请日：1987-05-14

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  MATSUMOTO YOSHIO

IPC: H04L29/06 ,  G06F13/00 ,  H04L13/00 ,  H04L29/08

Abstract: PURPOSE:To omit a control step to instruct a writing reading with a command, etc., and to execute the high speed of a transmission system by providing the status bit of writing and reading uttered automatically from a processor side to the internal part of a data column serially transmitted. CONSTITUTION:At a CPU (processor) 10 of a prescribed bit, respective output terminals of a writing control signal WR, a reading control signal RD, a memory access requesting signal MERQ, 16-bit addresses A0-A15 and respective input output terminals of 8-bit data D0-D7 are provided. The data from the CPU 10 are serially transmitted through a serial interface circuit 20 to plural controlled devices 11,12.... By an address decoder 22 of the circuit 20, an address allocated to the devices 11, 12... is detected. The parallel data inputted by a shift register 21 are converted to serial data, 3 state buffers 23 and the register 21 are controlled by a serial control circuit 24 and a step to instruct the writing reading is omitted.

公开(公告)号：JPS61175799A

公开(公告)日：1986-08-07

申请号：JP1554985

申请日：1985-01-31

Applicant: SONY CORP

Inventor： MATSUMOTO YOSHIO ,  TAWARA MORIYASU

IPC: H04Q9/16 ,  G08C19/22 ,  H04Q9/14