公开(公告)号：JPS5723268A

公开(公告)日：1982-02-06

申请号：JP9783680

申请日：1980-07-17

Applicant: Sony Corp

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA

IPC: H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  H01L29/76

CPC classification number: H01L27/1055

Abstract: PURPOSE:To prevent the lowering of the dynamic range in the BDD, the lowering of the signal level and the like, by making the floating capacitance value in the stage where an output circuit is connected with the side of the hot end of a capacitance smaller than the floating capacitance values of the other stages. CONSTITUTION:Inside of a plurality of N-type regions 33 junction-separated from a P-substrate, an NPN transistor Q and a capacitance C are formed. The transistors in the adjacent regions are connected in a series with an emitter terminal and collector terminal, and base terminals connected to a metal electrode 38 of the capacitance are alternately connected with two-phase clock terminals to constitute a BBD circuit. Among the circuits of the respective stages, the region 33 of the circuit to be furnished with a terminal Y connecting with the output circuit is made smaller than the region 33 (shown in dotted line) of the other stage to cancel the increase of the floating capacitance to be added by the connected ouput circuit. Thereby, the influence of the floating capacitance in the output stage can be removed to stabilize the operation of the electric charge transfer circuit.

Abstract translation: 目的：为了防止BDD中的动态范围的降低，信号电平的降低等，通过使输出电路与电容器的热端侧的连接较小的阶段中的浮动电容值较小 比其他级的浮动电容值。 构成：形成与P基板结合分离的多个N型区域33内的NPN晶体管Q和电容C。 相邻区域中的晶体管与发射极端子和集电极端子串联连接，并且连接到电容器的金属电极38的基极端子与两相时钟端子交替连接以构成BBD电路。 在各级的电路中，与设置有与输出电路连接的端子Y的电路的区域33小于另一级的区域33（虚线所示），以抵消浮动的增加 由连接的输出电路添加的电容。 由此，可以消除输出级中的浮动电容的影响，以稳定电荷转移电路的工作。

公开(公告)号：JPS575422A

公开(公告)日：1982-01-12

申请号：JP7930680

申请日：1980-06-12

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA

IPC: H03H15/02

Abstract: PURPOSE:To reduce the leakage of signal between filters, by providing a separate clock driving circuit to a plurality of transversal filters. CONSTITUTION:A clock signal phi1' from a clock oscillator 18 is applied to each input terminal 16 of clock driving circuits 15a, 15b, 15c, and a clock signal phi2' from the clock oscillator 18 is given to each input terminal 16' of clock driving circuits 15a', 15b', 15c'. Further, clock signals phi1, phi2 from the clock driving circuits 15a, 15a' are respectively applied to clock input terminals 6a, 7a of a BBD of a filter Fa and the clock signals phi1, phi2 from the clock driving circuits 15b, 15b' are respectively given to clock input terminals 6b, 7b of a filter Fb. Further, the clock signals phi1, phi2 from clock driving circuits 15c, 15c' are respectively applied to clock input terminals 6c, 7c of a filter Fc. Of course, the clock line of the BBD of the filters Fa, Fb, Fc is made independent. A leakage signal is reduced to 1/hfe by an independent clock driving circuit.

公开(公告)号：JPS56163592A

公开(公告)日：1981-12-16

申请号：JP6626880

申请日：1980-05-19

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L29/762

Abstract: PURPOSE:To prevent the level fluctuation caused by the floating capacity, the current amplification factor or the like, by dividing the capacity at an optional stage of a charge transfer element with a rate according to the sensitivity coefficient and deciding the capacity value of a capacitor that compensates the difference of DC component at an output circuit in consideration of the transfer efficiency of a transistor. CONSTITUTION:The figure shows a noncyclic trnsversal filter using a BBD. The division coefficient of each capacitor is set [(C+Cs)/C]X(1/alpha)X(1/delta)X(1/alpha') times as much as the value that is originally required. Here C is the transfer capacity value forming a charge transfer element (CTD), Cs is the floating capacity value, alpha is the base-earthed current amplification factor of a detecting transistor, delta is the transmission coefficient of a current Miller circuit M1, alpha' is the base-earthed current amplification factor of a transistor forming a CTD, and n is the number of transistors forming the CTDs up to an output capacitor. At the same time, the point of connection between transistors 11 and 12 is earthed via a capacitor 20 having a prescribed capacity CA so that the DC component caused by the floating capacity is offset.

公开(公告)号：JPS5683112A

公开(公告)日：1981-07-07

申请号：JP16008379

申请日：1979-12-10

Applicant: SONY CORP

Inventor： TSUCHIYA TAKAHISA ,  SONEDA MITSUO ,  NAKAMURA ISA

IPC: H03H15/02 ,  H03K5/00 ,  H03K5/02 ,  H03K17/04

Abstract: PURPOSE:To increase the frequency of clock signal, by obtaining an output without delay time, through the supply of the current multiplied by the current amplification factor for the signal current to the base of opposing transistors in the current Miller circuit. CONSTITUTION:Transistors (TR)11, 12 and charge transfer element BBD are provided, the collector of TR12 is connected to the base of a npn TR21, the emitter of TR21 is to the base and collector of npn TR22, and the base of TR22 is connected to the base of npn TR24. In such a circuit, with signals phi2 and phi1 respectively at voltage VDC and voltage VDC+VP, when a current flows via TR12, TR21, is on and a current multiplied by the current amplification factor hFE of the signal current is given to the base of TRs22 and 24. Then, TRs22 and 24 immediately turn on, and after that, a current equal to that flowing to TR24 is output 26 via TR22, the same as conventional current Miller circuits. Thus, the output without delay time is obtained to enable to increase the frequency of the clock signal.