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    Switching circuit
    2.
    发明授权
    Switching circuit 失效
    开关电路

    公开(公告)号：US3892983A

    公开(公告)日：1975-07-01

    申请号：US39930573

    申请日：1973-09-21

    Applicant: SONY CORP

    Inventor： OKADA TAKASHI ,  NAKAMURA ISA

    IPC: H04B1/10 ,  H03F3/72 ,  H03K17/60 ,  H03K17/62 ,  H04N9/71 ,  H03F1/00

    CPC classification number: H04N9/71 ,  H03F3/72 ,  H03K17/60

    Abstract: A switching circuit in which the signal path between a signal input and a signal output terminal includes at least two amplifier stages, the first one of which has its collector connected in a series circuit with a load impedance and the emitter-collector circuit of a switching transistor. The switching transistor is switched between a conductive and a nonconductive state by a switching voltage applied to its base. The base of a second amplifier stage is connected between the collector of the first stage and the load so that when the switching transistor is made non-conductive by preventing current from flowing in its emitter-collector circuit but also makes the second stage non-conductive by reducing its base current to zero. Making the first stage non-conductive keeps it from amplifying the signal and requires any leakage current to pass around the first stage by means of stray capacitance. Making the first and second stages non-conductive simultaneously prevents even the leakage current from being amplified and allows the leakage current to reach the output terminal only by way of a second stray capacitance, which further reduces the amplitude of such current. A cascode stage may be included between the first and second stages to be rendered non-conductive along with them as a further means of amplifying the signal when the transistors are operative and decoupling the signal when the transistors are nonconductive. Instead of a simple cascode stage, a differential amplifier stage may be included between the first and second stages to provide means for adjusting the gain of the circuit.

    Abstract translation: 一种开关电路，其中信号输入端和信号输出端之间的信号路径包括至少两个放大级，其中第一放大级的集电极连接在具有负载阻抗的串联电路中，并且发射极 - 集电极电路的开关 晶体管。 开关晶体管通过施加到其基极的开关电压在导通状态和非导通状态之间切换。 第二放大器级的基极连接在第一级的集电极和负载之间，使得当开关晶体管通过防止电流在其发射极 - 集电极电路中流动而变得不导通，而且使第二级不导通 通过将其基极电流减小到零。 使第一级不导通，使其不会放大信号，并且需要任何漏电流通过杂散电容通过第一级。 使第一和第二级不导通同时防止漏电流被放大，并且允许泄漏电流仅通过第二杂散电容到达输出端，这进一步减小了这种电流的幅度。 可以将第一和第二级之间的共源共栅级包括在与它们一起变得不导通的同时，作为当晶体管工作时放大信号并在晶体管不导通时对信号进行去耦的另一种手段。 代替简单的共源共栅级，可以在第一级和第二级之间包括差分放大器级，以提供用于调整电路的增益的装置。

    BUCKET BRIGADED DEVICE
    3.
    发明专利
    BUCKET BRIGADED DEVICE 未知

    公开(公告)号：AU533397B2

    公开(公告)日：1983-11-24

    申请号：AU6478280

    申请日：1980-11-27

    Applicant: SONY CORP

    Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO ,  NAKAMURA ISA

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L29/762 ,  H03H11/26 ,  H03H15/00 ,  H03K5/135 ,  H03K5/14 ,  H03K5/159

    Abstract: A bucket brigaded device is provided which includes first and second clocking signal generators for generating a first set and a second set of clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge levels from one capacitor to another. Each of the transistors is connected between adjacent capacitors. The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of clocking signals to each capacitor, and a second clocking signal driver for supplying one of the second set of clocking signals to each transistor.

    BUCKET BRIGADED DEVICE
    5.
    发明专利
    BUCKET BRIGADED DEVICE 未知

    公开(公告)号：CA1147817A

    公开(公告)日：1983-06-07

    申请号：CA365672

    申请日：1980-11-27

    Applicant: SONY CORP

    Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO ,  NAKAMURA ISA

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L29/762 ,  H03K3/36

    Abstract: A bucket brigaded device is provided which includes a first and second clocking signal generators for generating first set and second set of plural clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge from one capacitor to another. Each of the transistors is connected between adjacent capacitors. The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of plural clocking signals to the capacitor, and a second clocking signal driver for supplying one of the second set of plural clocking signals to the transitor.

    6.
    发明专利
    未知

    公开(公告)号：FR2471653A1

    公开(公告)日：1981-06-19

    申请号：FR8025703

    申请日：1980-12-03

    Applicant: SONY CORP

    Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO ,  NAKAMURA ISA

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L29/762

    Abstract: A bucket brigaded device is provided which includes first and second clocking signal generators for generating a first set and a second set of clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge levels from one capacitor to another. Each of the transistors is connected between adjacent capacitors. The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of clocking signals to each capacitor, and a second clocking signal driver for supplying one of the second set of clocking signals to each transistor.

    8.
    发明专利
    未知

    公开(公告)号：DE3045466A1

    公开(公告)日：1981-08-27

    申请号：DE3045466

    申请日：1980-12-02

    Applicant: SONY CORP

    Inventor： TSUCHIYA TAKAO ,  SONEDA MITSUO ,  NAKAMURA ISA

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/339 ,  H01L29/762 ,  H03H15/02

    Abstract: A bucket brigaded device is provided which includes first and second clocking signal generators for generating a first set and a second set of clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge levels from one capacitor to another. Each of the transistors is connected between adjacent capacitors. The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of clocking signals to each capacitor, and a second clocking signal driver for supplying one of the second set of clocking signals to each transistor.

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