公开(公告)号：JPH0969605A

公开(公告)日：1997-03-11

申请号：JP24665295

申请日：1995-08-31

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU ,  NAKAMURA MITSUHIRO ,  WADA SHINICHI ,  TANAKA KUNINOBU ,  YASUSHIGE HIROAKI

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a thin film capacitance element and its manufacturing method wherein the capacitance per occupied area of a semiconductor substrate is increased and dispersion in capacitance and short-circuit defects are suppressed. SOLUTION: An insulation film 2 is provided on a semiconductor substrate 1 having an even surface, and a thin film electrode 3a is provided on it. A bump electrode 3b is selectively provided on the thin film electrode 3a, and the thin film electrode 3a and the bump electrode 3b constitute a lower electrode 3. An insulation film 4 and an upper layer electrode 5 are laminated on the lower electrode 3 in this order, thus an MIM capacitor is constituted.

公开(公告)号：JPH02152381A

公开(公告)日：1990-06-12

申请号：JP30579788

申请日：1988-12-02

Applicant: SONY CORP

Inventor： NAKAMURA MITSUHIRO ,  TAKAHASHI YASUSHI ,  TSURUMOTO TAKASHI

IPC: H04N5/445 ,  H04N5/46

Abstract: PURPOSE:To prevent baking due to pattern by displaying a prescribed pattern whose brightness is changed at random to a blank part caused in the case of displaying a picture of the existing standard broadcast in a TV receiver whose aspect ratio is 16:9. CONSTITUTION:A high definition TV signal VHD is inputted to an input terminal 1 and a standard TV signal VNT is fed to an input terminal 2. A tie axis conversion circuit 5 compresses a video period TV1 in the horizontal direction of a signal VNT into a video period TV2 and blank periods T1, T2 are provided to both ends of the horizontal period and a switch control signal SW is outputted. Moreover, a pattern generating circuit 7 outputs a pattern whose brightness changes at random. A switch circuit 6 is switched to the position of a contact (a) at the video period TV2 and switched to the position of a contact (b) at the blank periods T1, T2 added with the pattern. Then the output of the circuit 6 is fed to a receiver 10 via the position (b) of the switch circuit 4.

公开(公告)号：JP2013081691A

公开(公告)日：2013-05-09

申请号：JP2011224792

申请日：2011-10-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： WADA SEIJI ,  YAMAMOTO TAKUO ,  SOMA ATSUHIKO ,  NAKAJIMA YUSAKU ,  TOMITA TAKASHI ,  NAKAMURA MITSUHIRO ,  KIMURA NAGETSU

IPC: A61B5/16 ,  A61B5/0402 ,  A61B5/0408 ,  A61B5/0476 ,  A61B5/0478 ,  A61B5/0488 ,  A61B5/087 ,  A61B5/11 ,  A61B5/1455

CPC classification number: A61B5/0006 ,  A61B5/0205 ,  A61B5/04012 ,  A61B5/0402 ,  A61B5/0408 ,  A61B5/0478 ,  A61B5/0496 ,  A61B5/087 ,  A61B5/1135 ,  A61B5/14542 ,  A61B5/4806 ,  A61B5/4812 ,  A61B5/4818 ,  A61B5/6803 ,  A61B2562/06

Abstract: PROBLEM TO BE SOLVED: To provide a PSG test device appropriate for home monitoring.SOLUTION: The PSG-test headgear includes an electroencephalogram electrode and an electrooculogram electrode and an oxygen saturation sensor. The electroencephalogram electrode obtains the electroencephalogram of a user. The electrooculogram electrode obtains the electrooculogram of the user. The oxygen saturation sensor obtains the oxygen saturation level of the user. PSG test device further has a PSG test chest brace having a chin electromyogram electrode to obtain a chin electromyogram, an airflow sensor which obtains nasal and mouth breathing, an electrocardiogram sensor to obtain an electrocardiogram and a respiratory movement sensor which obtains respiratory movement.

Abstract translation: 要解决的问题：提供适合家庭监控的PSG测试设备。 解决方案：PSG测试头盔包括脑波电极和电脉冲电极和氧饱和度传感器。 脑波电极获得使用者的脑电图。 电脉冲电极获得用户的电文图。 氧饱和度传感器获得用户的氧饱和度水平。 PSG测试装置还具有具有下巴肌电图电极的PSG测试胸部支架，以获得下巴肌电图，获得鼻和嘴呼吸的气流传感器，获得心电图的心电图传感器和获得呼吸运动的呼吸运动传感器。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011039810A

公开(公告)日：2011-02-24

申请号：JP2009187044

申请日：2009-08-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ANZAI TETSUNOSHIN ,  HIGASHIKAWA TOSHIMITSU ,  NAKAMURA MITSUHIRO

IPC: G06K17/00 ,  H04B1/59

Abstract: PROBLEM TO BE SOLVED: To accurately obtain waiting time up to command retransmission from a controller. SOLUTION: After card command transmission processing, a reader/writer calculates total waiting time and transmits the calculated total waiting time to a controller 11 as an accepted packet (step S13). Concretely, the reader/writer calculates card waiting time by adding card command transmission processing time to the maximum response waiting time of card response. Further, the reader/writer calculates total waiting time according to following formula: total wait time = card waiting time × (retrial frequency +1)+ card access response generation time. This invention can be applied to a non-contact communication system. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：准确地获取从控制器发出命令的等待时间。 解决方案：在卡命令发送处理之后，读写器计算总等待时间，并将所计算的总等待时间作为接受的分组发送到控制器11（步骤S13）。 具体地，读写器通过将卡命令发送处理时间添加到卡响应的最大响应等待时间来计算卡等待时间。 此外，读写器根据以下公式计算总等待时间：总等待时间=卡等待时间×（重试频率+1）+卡访问响应生成时间。 本发明可以应用于非接触式通信系统。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009159606A

公开(公告)日：2009-07-16

申请号：JP2008311284

申请日：2008-12-05

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUKUMA YOHEI ,  HOSODA IKUHIDE ,  NAKAMURA MITSUHIRO ,  OBA HARUO

IPC: H04N5/225

Abstract: PROBLEM TO BE SOLVED: To provide an imaging apparatus for miniaturizing a chassis, and being superior in establishing a degree of freedom of designability while improving operability in imaging.
SOLUTION: The chassis 12 has an elongated shape, wherein one of surfaces in a thickness direction is a front surface 12A, and the other surface in the thickness direction is a rear surface 12B which is parallel to the front surface 12A. An imaging optical system 14 includes an objective lens 14A which is located nearest to an object side, wherein the objective lens 14A is provided at a portion near one end portion in a longitudinal direction of the chassis 12. A shutter button 25 is provided on the same surface as a surface (front surface 12A) of the chassis 12 wherein the objective lens 14A is provided, and at a portion of the other end side in a longitudinal direction of the chassis 12 nearer than the objective lens 14A at near the objective lens 14A.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于使底盘小型化的成像装置，并且在提高成像的可操作性的同时优良地设计可设计性的自由度。 解决方案：底盘12具有细长形状，其中厚度方向上的一个表面是前表面12A，厚度方向上的另一个表面是与前表面12A平行的后表面12B。 成像光学系统14包括最靠近物体侧的物镜14A，其中物镜14A设置在靠近底盘12的纵向方向上的一个端部附近的部分。快门按钮25设置在 与设置有物镜14A的底座12的表面（前表面12A）相同的表面，以及在靠近物镜的情况下在底架12的比物镜14A更靠近的纵向方向的另一端侧的一部分 14A。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008218461A

公开(公告)日：2008-09-18

申请号：JP2007049524

申请日：2007-02-28

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAGUCHI TADAHISA ,  KUBO HIROYUKI ,  NAKAMURA MITSUHIRO ,  TAMATOSHI SHINICHI

IPC: H01L21/337 ,  H01L29/808

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a field effect transistor and the field effect transistor which can reduce IMD (intermodulation distortion), and to provide a semiconductor device equipped with this field effect transistor and a communication apparatus.
SOLUTION: This field effect transistor 1 has a buried gate region 5 formed by doping an impurity in a compound semiconductor substrate 19, wherein concave portions 6L and 6R are provided on both the sides of the buried gate region 5 of the compound semiconductor substrate 19.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可以减小IMD（互调失真）的场效应晶体管和场效应晶体管的制造方法，并提供配备有该场效应晶体管和通信装置的半导体器件。 解决方案：该场效应晶体管1具有通过在化合物半导体衬底19中掺杂杂质而形成的掩埋栅极区域5，其中凹部6L和6R设置在化合物半导体的掩埋栅极区域5的两侧 底漆19.版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007304849A

公开(公告)日：2007-11-22

申请号：JP2006132511

申请日：2006-05-11

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKAMURA MITSUHIRO ,  NAKAMURA ATSUSHI ,  KAWAMOTO HIROSHI ,  FUTAGAMI KISEI ,  ADACHI SEIICHI

IPC: G06F21/00 ,  G06F21/10 ,  G06F21/34 ,  G06F21/62 ,  G06Q50/00 ,  G06Q50/10 ,  H04L9/08

CPC classification number: G06F21/10 ,  G06F2221/0706

Abstract: PROBLEM TO BE SOLVED: To provide a management server, information processor, management method, and information processing method for protecting copyright of a content. SOLUTION: A management server 20 is provided with: a group management part 232 for registering one or more information processor 30 owned by an identical user in one group and distributing a user key granted uniquely to the group-registered information processor for each user; a licence issuing part 238 for issuing a license obtained by encrypting a use condition of the content and a content key for decoding an encrypted content with the user key in response to a request from the information processors; and a right information issuing part 260 for issuing right information to permit use of the content based on the license in a specific use form to an information processor whose use in the specific use form is permitted among group-registered information processors. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于保护内容的版权的管理服务器，信息处理器，管理方法和信息处理方法。 管理服务器20具有：组管理部件232，用于将一个或多个相同用户拥有的一个或多个信息处理器30注册在一个组中，并且将针对每个组分配唯一地授予组组注册信息处理器的用户密钥 用户; 响应于来自信息处理器的请求，发出通过加密内容的使用条件获得的许可证的许可证发放部分238和用于使用用户密钥解密加密的内容的内容密钥; 以及权利信息发布部分260，用于发布权限信息以允许以特定使用形式基于许可证使用内容到在组注册的信息处理器中允许以特定使用形式使用的信息处理器。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005039084A

公开(公告)日：2005-02-10

申请号：JP2003275310

申请日：2003-07-16

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKAMURA MITSUHIRO

IPC: H01L27/04 ,  G06G7/12 ,  H01L21/06 ,  H01L21/335 ,  H01L21/338 ,  H01L21/822 ,  H01L21/8232 ,  H01L27/06 ,  H01L27/095 ,  H01L29/778 ,  H01L29/812 ,  H03F1/30 ,  H03F3/16

CPC classification number: H03F1/301

Abstract: PROBLEM TO BE SOLVED: To provide a bias circuit for uniformly suppressing bias currents even when the threshold voltage of a transistor fluctuates.
SOLUTION: A resistance element R1 whose resistance value fluctuates while being linked with the threshold of a transistor FET1 is connected between a gate bias supply terminal T3 and a gate terminal G. Even when the threshold of the transistor FET1 fluctuates, the resistance value is increased/decreased according to the increase/decrease of the threshold. When the threshold is increased, the resistance value is decreased, and a bias voltage is adjusted so as to be increased according to a resistance partial pressure. When the threshold is decreased, the resistance value is increased, and the bias voltage is adjusted so as to be decreased according to the resistance partial pressure. The transistor FET1 is constituted as a junction transistor having a first conductive channel and a second conductive gate, and a resistance element R1 is manufactured by a second conductive type semiconductor area.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：即使当晶体管的阈值电压波动时，也提供用于均匀抑制偏置电流的偏置电路。 解决方案：在栅极偏置电源端子T3和栅极端子G之间连接电阻值与晶体管FET1的阈值相关的电阻值波动的电阻元件R1。即使当晶体管FET1的阈值波动时，电阻 值根据阈值的增加/减少而增加/减少。 当阈值增加时，电阻值减小，并且偏置电压被调整为根据电阻分压而增加。 当阈值降低时，电阻值增加，并且偏置电压被调整为根据电阻分压而减小。 晶体管FET1构成为具有第一导电沟道和第二导电栅极的结型晶体管，电阻元件R1由第二导电型半导体区域制造。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003031593A

公开(公告)日：2003-01-31

申请号：JP2001215276

申请日：2001-07-16

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKAMURA MITSUHIRO

IPC: H01L21/28 ,  H01L21/338 ,  H01L29/417 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has high productivity, even though the device can operate at a high speed and at high frequencies, and to provide its manufacturing method.
SOLUTION: A sidewall 12b, of an end edge 12a of an insulation film 12 on a semiconductor substrate 11, is provided with a compound film 15 of a conductor element and a metal element, and this compound film 15 serves as a gate. The compound film 15 can be formed matching itself with the sidewall 12b, by using semiconductor elements in the insulation film 12, semiconductor elements of a semiconductor film formed on the side wall 12b without using masks, etc. Consequently, the length of a gate can be set at right angles with respect to the sidewall 12b, and then when the gate is formed, application of lithography for prescribing the gate length is not necessary, so that a fine gate can be formed easily without using special exposure apparatus for fine processing.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：即使设备能够以高速和高频率操作，也提供了具有高生产率的半导体器件，并提供其制造方法。 解决方案：半导体基板11上的绝缘膜12的端边缘12a的侧壁12b设置有导体元件和金属元件的复合膜15，该复合膜15用作栅极。 复合膜15可以通过使用绝缘膜12中的半导体元件，形成在侧壁12b上的半导体膜的半导体元件而不使用掩模等，而使其与侧壁12b自身匹配。因此，栅极的长度 相对于侧壁12b成直角设置，然后当形成栅极时，不需要施加用于规定栅极长度的光刻，从而可以容易地形成精细的栅极，而不需要使用专门的微细处理的曝光装置。

公开(公告)号：JPH11274468A

公开(公告)日：1999-10-08

申请号：JP7720198

申请日：1998-03-25

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OGURA MITSUMASA ,  MURAKAMI MASANORI ,  NAKAMURA MITSUHIRO

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45

CPC classification number: H01L21/28575 ,  H01L29/452

Abstract: PROBLEM TO BE SOLVED: To realize an ohmic electrode having characteristics which are practically satisfactory for a GaAs-base semiconductor or the like.
SOLUTION: A Ni thin film 3 having a thickness of 8 to 30 nm, an In thin film 4 having a thickness of 2 to 6 nm, and a Ge thin film 5 having a thickness of 10 to 50 nm are formed in a predetermined pattern on an n
+ -type GaAs substrate 1, and then the n
+ -type GaAs substrate 1 on which the Ni thin film 3, the In thin film 4, and the Ge thin film 5 are formed is subjected to a heat treatment at 300 to 600°C for several seconds to several minutes to form an ohmic electrode having a laminated structure including an n
++ -type GaAs layer 6 which is further grown from the n
+ -type GaAs substrate 1, an InGaAs layer 7, and a NiGe thin film 8; or a high-melting metal thin film like a Nb thin film or a thin film made of the compound of the metal is formed further on the Ge thin film 5, or a thin film made of wiring metal like an Au thin film is further formed thereon, and then the n
+ -type GaAs substrate 1 is subjected to a heat treatment to form an ohmic electrode.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了实现对于GaAs基半导体等具有实际满意的特性的欧姆电极。 解决方案：以预定图案形成厚度为8至30nm的Ni薄膜3，厚度为2至6nm的In薄膜4和厚度为10至50nm的Ge薄膜5 在n +型GaAs衬底1上，然后对其上形成有Ni薄膜3，In薄膜4和Ge薄膜5的n +型GaAs衬底1进行 在300〜600℃下热处理数秒〜数分钟以形成具有层叠结构的欧姆电极，该层叠结构包括从n +型GaAs衬底进一步生长的n ++型GaAs层6 1，InGaAs层7和NiGe薄膜8; 或者在Ge薄膜5上进一步形成像Nb薄膜或由金属化合物构成的薄膜的高熔点金属薄膜，或进一步形成由诸如Au薄膜的布线金属制成的薄膜 然后对n +型GaAs衬底1进行热处理以形成欧姆电极。