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公开(公告)号：CA1203855A
公开(公告)日：1986-04-29
申请号：CA446138
申请日：1984-01-26
Applicant: SONY CORP
Inventor： ISHIKAWA FUMIO , TANAKA KUNINOBU
Abstract: A buffer circuit having a main buffer circuit section formed of a pair of complementary input side transistors the bases of which are connected together and a dummy circuit section having the same circuit construction as the main buffer circuit section. A feedback signal formed on the basis of the output from the dummy circuit section is supplied to the dummy circuit section and the main buffer circuit section so as to make the output of the dummy circuit section equal to a predetermined value,
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公开(公告)号：DE69427378T2
公开(公告)日：2002-04-25
申请号：DE69427378
申请日：1994-01-07
Applicant: SONY CORP
Inventor： MAEKAWA ITARU , OHGIHARA TAKAHIRO , TANAKA KUNINOBU
Abstract: The present invention relates to a bias stabilizing circuit for a field effect transistor formed of a compound semiconductor comprising: a bias circuit in which one output electrode of a bipolar transistor (Q100, Q120, Q130, Q140) which is applied at its base with a bias voltage is connected through a first resistor (R103, R123, R132, R143) to a power supply (+B) and the other output electrode thereof is grounded through a second resistor (R104, R124, R133, R144); and a field effect transistor (102, 122, 132, 142) formed of a compound semiconductor biased by said bias circuit, wherein one output electrode (100D, 120D, 130D, 140D) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to one output electrode of said field effect transistor (102, 122, 132, 142) and the other output electrode (100G, 120G, 130G, 140G) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to a gate of said field effect transistor (102, 122, 132, 142).
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公开(公告)号：DE69420981D1
公开(公告)日：1999-11-11
申请号：DE69420981
申请日：1994-01-07
Applicant: SONY CORP
Inventor： MAEKAWA ITARU , OHGIHARA TAKAHIRO , TANAKA KUNINOBU
Abstract: The present invention relates to a bias stabilizing circuit for a field effect transistor formed of a compound semiconductor comprising: a bias circuit in which one output electrode of a bipolar transistor (Q100, Q120, Q130, Q140) which is applied at its base with a bias voltage is connected through a first resistor (R103, R123, R132, R143) to a power supply (+B) and the other output electrode thereof is grounded through a second resistor (R104, R124, R133, R144); and a field effect transistor (102, 122, 132, 142) formed of a compound semiconductor biased by said bias circuit, wherein one output electrode (100D, 120D, 130D, 140D) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to one output electrode of said field effect transistor (102, 122, 132, 142) and the other output electrode (100G, 120G, 130G, 140G) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to a gate of said field effect transistor (102, 122, 132, 142).
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公开(公告)号：DE69427311T2
公开(公告)日：2001-11-22
申请号：DE69427311
申请日：1994-01-07
Applicant: SONY CORP
Inventor： MAEKAWA ITARU , OHGIHARA TAKAHIRO , TANAKA KUNINOBU
Abstract: The present invention relates to a bias stabilizing circuit for a field effect transistor formed of a compound semiconductor comprising: a bias circuit in which one output electrode of a bipolar transistor (Q100, Q120, Q130, Q140) which is applied at its base with a bias voltage is connected through a first resistor (R103, R123, R132, R143) to a power supply (+B) and the other output electrode thereof is grounded through a second resistor (R104, R124, R133, R144); and a field effect transistor (102, 122, 132, 142) formed of a compound semiconductor biased by said bias circuit, wherein one output electrode (100D, 120D, 130D, 140D) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to one output electrode of said field effect transistor (102, 122, 132, 142) and the other output electrode (100G, 120G, 130G, 140G) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to a gate of said field effect transistor (102, 122, 132, 142).
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公开(公告)号：DE3470263D1
公开(公告)日：1988-05-05
申请号：DE3470263
申请日：1984-01-27
Applicant: SONY CORP
Inventor： ISHIKAWA FUMIO , TANAKA KUNINOBU
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Patent Agency Ranking
公开(公告)号：DE69427378D1
公开(公告)日：2001-07-05
申请号：DE69427378
申请日：1994-01-07
Applicant: SONY CORP
Inventor： MAEKAWA ITARU , OHGIHARA TAKAHIRO , TANAKA KUNINOBU
Abstract: The present invention relates to a bias stabilizing circuit for a field effect transistor formed of a compound semiconductor comprising: a bias circuit in which one output electrode of a bipolar transistor (Q100, Q120, Q130, Q140) which is applied at its base with a bias voltage is connected through a first resistor (R103, R123, R132, R143) to a power supply (+B) and the other output electrode thereof is grounded through a second resistor (R104, R124, R133, R144); and a field effect transistor (102, 122, 132, 142) formed of a compound semiconductor biased by said bias circuit, wherein one output electrode (100D, 120D, 130D, 140D) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to one output electrode of said field effect transistor (102, 122, 132, 142) and the other output electrode (100G, 120G, 130G, 140G) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to a gate of said field effect transistor (102, 122, 132, 142).
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公开(公告)号：DE69427311D1
公开(公告)日：2001-06-28
申请号：DE69427311
申请日：1994-01-07
Applicant: SONY CORP
Inventor： MAEKAWA ITARU , OHGIHARA TAKAHIRO , TANAKA KUNINOBU
Abstract: The present invention relates to a bias stabilizing circuit for a field effect transistor formed of a compound semiconductor comprising: a bias circuit in which one output electrode of a bipolar transistor (Q100, Q120, Q130, Q140) which is applied at its base with a bias voltage is connected through a first resistor (R103, R123, R132, R143) to a power supply (+B) and the other output electrode thereof is grounded through a second resistor (R104, R124, R133, R144); and a field effect transistor (102, 122, 132, 142) formed of a compound semiconductor biased by said bias circuit, wherein one output electrode (100D, 120D, 130D, 140D) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to one output electrode of said field effect transistor (102, 122, 132, 142) and the other output electrode (100G, 120G, 130G, 140G) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to a gate of said field effect transistor (102, 122, 132, 142).
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公开(公告)号：DE69420981T2
公开(公告)日：2000-04-06
申请号：DE69420981
申请日：1994-01-07
Applicant: SONY CORP
Inventor： MAEKAWA ITARU , OHGIHARA TAKAHIRO , TANAKA KUNINOBU
Abstract: The present invention relates to a bias stabilizing circuit for a field effect transistor formed of a compound semiconductor comprising: a bias circuit in which one output electrode of a bipolar transistor (Q100, Q120, Q130, Q140) which is applied at its base with a bias voltage is connected through a first resistor (R103, R123, R132, R143) to a power supply (+B) and the other output electrode thereof is grounded through a second resistor (R104, R124, R133, R144); and a field effect transistor (102, 122, 132, 142) formed of a compound semiconductor biased by said bias circuit, wherein one output electrode (100D, 120D, 130D, 140D) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to one output electrode of said field effect transistor (102, 122, 132, 142) and the other output electrode (100G, 120G, 130G, 140G) of said bipolar transistor (Q100, Q120, Q130, Q140) is connected to a gate of said field effect transistor (102, 122, 132, 142).
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公开(公告)号：CA1210086A
公开(公告)日：1986-08-19
申请号：CA455254
申请日：1984-05-28
Applicant: SONY CORP
Inventor： ISHIKAWA FUMIO , TANAKA KUNINOBU
Abstract: A two phase voltage signal generating circuit for generating a pair of trapezoidal wave signals of phases opposite to each other is disclosed which includes an input terminal supplied with an input pulse signal, a capacitor, a pair of voltage limiting circuits connected to both ends of the capacitor respectively and for limiting the voltage at each end of the capacitor within a predetermined voltage range, a current control circuit controlled by the input pulse signal and for supplying a charge or discharge current to the capacitor to generate the pair of trapezoidal wave voltage of the trapezoidal wave voltage signals and a symmetry control circuit controlled by an output of the detecting circuit and for controlling the charge or discharge current such that the pair of trapezoidal wave voltage signals become substantially symmetrical to each other.
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公开(公告)号：JP2002007981A
公开(公告)日：2002-01-11
申请号：JP2000184704
申请日：2000-06-20
Applicant: SONY CORP
Inventor： TANAKA KUNINOBU
Abstract: PROBLEM TO BE SOLVED: To provide an information recording medium for recording various information and an information reproducing device for reproducing the recorded information on the information recording medium. SOLUTION: A number of transmitting holes corresponding to predetermined recorded information are selectively formed on a flat plate made of a lightproof material. Light transmittance at each transmitting hole is detected and the formed position of each transmitting hole is read, and the recorded information is reproduced from the formed position.
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