公开(公告)号：WO2016092762A2

公开(公告)日：2016-06-16

申请号：PCT/JP2015005906

申请日：2015-11-27

Applicant: SONY CORP

Inventor： SAKANO YORITO ,  IMOTO TSUTOMU ,  NOMURA HIDEO ,  TASHIRO YOSHIAKI ,  NISHIHARA TOSHIYUKI ,  COHEN MURIEL ,  BRADY FREDERICK

IPC: H01L27/146 ,  H04N3/14

CPC classification number: H04N5/3594 ,  H01L27/14601 ,  H01L27/1461 ,  H01L27/14612 ,  H04N5/3575 ,  H04N5/3591 ,  H04N5/3745 ,  H04N5/37455 ,  H04N5/378

Abstract: An imaging apparatus with logarithmic characteristics includes: a photodiode that receives light; a well tap unit that fixes the potential of an N-type region of the photodiode; and a resetting unit that resets the photodiode, a P-type region of the photodiode outputting a voltage signal equivalent to a photocurrent subjected to logarithmic compression. The first potential to be supplied to the well tap unit is made lower than the second potential to be supplied to the resetting unit, so that the capacitance formed with the PN junction of the photodiode is charged when the resetting unit performs a reset operation. The present technology can be applied to unit pixels having logarithmic characteristics.

Abstract translation: 具有对数特性的成像设备包括：接收光的光电二极管; 固定光电二极管的N型区域的电势的阱分支单元; 以及复位单元，复位光电二极管，光电二极管的P型区域输出与受到对数压缩的光电流等效的电压信号。 使提供给阱抽头部的第一电位低于提供给复位部的第二电位，使得在复位部进行复位动作时，由光电二极管的PN结形成的电容被充电。 本技术可以应用于具有对数特性的单位像素。

公开(公告)号：AU2003242433A1

公开(公告)日：2003-12-31

申请号：AU2003242433

申请日：2003-05-23

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU

IPC: G01N27/12 ,  G01N1/24 ,  G01N5/02 ,  G01N33/00 ,  G01N1/22

Abstract: A gas detector capable of accurately measuring particular components (odors or the like) contained in an ambient gas to be measured, being compact, and capable of being easily formed to be portable, or producing low noise and capable of being small-sized. Having zero gas cylinder ( 9 ) as a supplying unit of a zero gas and component parts disposed within its enclosure ( 2 ) and using syringe ( 3 ) as a gas intake/exhaust unit, it alternately introduces a test gas, i.e., an ambient gas taken in from outside enclosure ( 2 ) through piping ( 12 a), and the zero gas supplied from zero gas cylinder ( 9 ) into sensor unit ( 7 ) and measures the test gas, while having operation of each unit controlled by data processor ( 11 ). Thus, accurate measurement of the test gas is achieved by relatively comparing results of measurement on the gases at each measurement. In addition, gas detector ( 1 ) can be moved to a spot where measurement is to be made to have the test gas there measured. Further, by use of a cylinder mechanism producing low noise, the detector can quantify gas intake/exhaust and can be made small in size.

公开(公告)号：AU2003242431A1

公开(公告)日：2003-12-12

申请号：AU2003242431

申请日：2003-05-23

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU ,  ENOMOTO MASASHI

IPC: H01L31/04 ,  H01G9/20 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/052 ,  H01L51/00 ,  H01L51/30 ,  H01L51/44 ,  H01M14/00

公开(公告)号：AU2003254946A1

公开(公告)日：2004-03-11

申请号：AU2003254946

申请日：2003-08-19

Applicant: SONY CORP

Inventor： ODA MASAO ,  IMOTO TSUTOMU

IPC: H01L31/04 ,  H01G9/20 ,  H01M14/00

Abstract: A dye-sensitized photoelectric conversion apparatus having enhanced energy conversion efficiency and a production method thereof are provided. The dye-sensitized photoelectric conversion apparatus which has semiconductor layer (13) containing a photosensitizing dye (14) and is constituted such that a charge carrier generated by allowing light to incident in the photosensitizing dye (14) is drawn out through the semiconductor layer (13), in which the semiconductor layer (13) is constituted by a plurality of regions (13A to 13D) having different energy levels from one another of a passage through which the charge carrier is transferred. Further, the plurality of regions (13A to 13D) are arranged such that the energy levels are reduced stepwise and/or continuously in the direction of drawing the charge carrier out.

公开(公告)号：JP2002190481A

公开(公告)日：2002-07-05

申请号：JP2000386943

申请日：2000-12-20

Applicant: SONY CORP

Inventor： TONERIKAWA SUSUMU ,  IMOTO TSUTOMU

IPC: H01L27/04 ,  H01L21/337 ,  H01L21/338 ,  H01L21/822 ,  H01L29/808 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To reduce parasitic capacitance, while securing capacitance required for surge energy absorption and to simplify the manufacturing process. SOLUTION: On a GaAs substrate 3, an n+ type diffusion region 4 and a p+ type diffusion region 5 joined inside the n+ type diffusion region 4 are formed. A protective diode 1 and a GaAsJFET 2 are integrated, by respectively connecting a p-n junction electrode 20 of the protective diode 1 to a gate electrode 30 and a source electrode 31 of the GaAsJFET 2. In the n+ diffusion region 4a of the protective diode 1, an i-diffustion region 12 is formed at the bottom surface part of the n+ diffusion region 4a, by using an ion implantation method or the like. Thus, a p-n junction in the protective diode 1 is constituted of the side face of the p+ type diffusion region 16 and the n+ type diffusion region 4a.

公开(公告)号：JP2001077306A

公开(公告)日：2001-03-23

申请号：JP25105399

申请日：1999-09-06

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor device in which a resistance element and an electrode wiring layer three-dimensionally intersect each other, and which can prevent or suppress the fluctuation of the resistance value of the resistance element which may cause the malfunction of a circuit, by eliminating or reducing the influence of the potential at the wiring layer upon a resistance layer without increasing the area of the circuit, and to obtain a method for manufacturing the device. SOLUTION: In a semiconductor device, a resistance element which is composed mainly of an n--type resistance layer 105 formed on the surface of a semi-insulating GaAs substrate 101 is constituted. Above the resistance layer 105 of the resistance element, a Ti/At/Au wiring layer 117c three-dimensionally intersects the resistance element with first and second SiN insulating films 109 and 112 in between, but, between the second and first SiN films 112 and 109 in the intersecting area, a Ti/Pt/Au electric field shielding layer 110a having such a size that can completely contain the intersecting area is interposed.

公开(公告)号：JP2000340581A

公开(公告)日：2000-12-08

申请号：JP15273199

申请日：1999-05-31

Applicant: SONY CORP

Inventor： ONODERA KOJI ,  IMOTO TSUTOMU ,  NAKAMURA MITSUHIRO ,  TSUKAMOTO HIRONORI

IPC: H01L21/338 ,  H01L21/28 ,  H01L21/337 ,  H01L29/778 ,  H01L29/808 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a satisfactory conduction characteristic to a gate electrode by interposing a film, having properties to suppress increase in the electrical resistance between the gate electrode and a compound semiconductor layer. SOLUTION: On a substrate 101, a buffer layer 102, a spacer layer 103, and an electron feeding layer 104 are deposited in the order. In an ohmic electrode forming region of the electron feeding layer 104, a p-type impurity diffused layer 111 is formed, where an oxide film is easy to form. On the impurity diffused layer 111 and the electron feeding layer 104, an insulation film 106 made of silicon oxide is formed. In an ohmic electrode formation region of the insulation film 106, an ohmic electrode 112 which is a gate electrode is formed in an opening which is so formed as to reach the impurity diffused layer 111. Between the ohmic electrode 112 and the impurity diffused layer 111 which is a compound semiconductor layer, a high resistance preventing film 113 is formed so as to suppress the increase in the electrical resistance by the oxide film.

公开(公告)号：JP2000196029A

公开(公告)日：2000-07-14

申请号：JP37457298

申请日：1998-12-28

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU ,  WADA SHINICHI

IPC: H01L21/76 ,  H01L21/337 ,  H01L21/338 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/095 ,  H01L27/098 ,  H01L29/778 ,  H01L29/808 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To simply and with high reliability constitute a semiconductor device, having at least two FETs(field-effect transistors) whose threshold voltages Vth are different. SOLUTION: This semiconductor device has at least two first and second field-effect transistors whose threshold voltages are different in a common substrate 71. The gate of the first field-effect transistor is constituted of a p-n junction J1, and the gate of the second field-effect transistor is constituted a Schottky junction J2. Thus, the threshold voltages of the first and second field-effect transistors can be respectively set according to the depth of the p-n junction and the selection of the barrier potential of the Schottky junction.

公开(公告)号：JP2000196028A

公开(公告)日：2000-07-14

申请号：JP37456898

申请日：1998-12-28

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU

IPC: H01L21/76 ,  H01L21/338 ,  H01L27/095 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To constitute simply and with high reliability a semiconductor device, having at least two FETs(field-effect transistors) whose threshold voltages are different. SOLUTION: This semiconductor device has at least two first and second field-effect transistors whose threshold voltages are different in a common substrate 71. The gate of the first field-effect transistor is constituted of a non-alloyed Schottky junction J1, and the gate of the second field-effect transistor is constituted of alloyed Schottky junction J2. Thus, the field-effect transistors whose threshold voltages are different are constituted.

公开(公告)号：JP2000100829A

公开(公告)日：2000-04-07

申请号：JP27145998

申请日：1998-09-25

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU ,  ISHIAI YOSHINORI ,  KAMATA MIKIO

IPC: H01L29/808 ,  H01L21/285 ,  H01L21/335 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a junction field-effect transistor and a manufacturing method thereof, that can achieve low on-resistance, high maximum drain current, lineality with high transmitting gain, and a shorter gate, without the need for two kinds of positive and negative power sources. SOLUTION: An andoped GaAs layer 3, an n+-type GaAs layer 4, and an n-type GaAs layer 5 undergo epitaxial growth in this order via a GaAs buffer layer 2 on a semi-insulating GaAs substrate 1 to form a channel layer. A dispersion mask composed of SiNx film is formed on the n-type GaAs layer 5, and Zn is dispersed on the n-type GaAs layer 5 through the opening of the mask so as to form a p+-type gate region 6. A gate matallic layer is stacked on the dispersion mask and is patterned, so as to form a gate electrode 7 on the opening of the dispersion mask in a self-matching manner to the p+-type gate region 6.