公开(公告)号：JPS61222268A

公开(公告)日：1986-10-02

申请号：JP6431285

申请日：1985-03-28

Applicant: SONY CORP

Inventor： WADA MASARU ,  ITSUNOI KATSUAKI ,  KATO YOJI

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/04 ,  H01L29/80

Abstract: PURPOSE:To prevent the intensifying of a short channel effect even if the length of a gate is shortened, by directing the orientation of a gate electrode so that the direction of the width of the gate is made to be the forward mesa direction. CONSTITUTION:The direction of the widths of the gate of a J-FET gate 5 and a gate electrode 6, which are formed on a (100) plane (a) of a GaAs substrate 1, is set so that said direction is made to be the forward mesa direction (b). The forward mesa direction is referred to be the direction, in which a recess part that is yielded by partial etching of the surface of the GaAs substrate 1 is expanded toward the deep part. Thus, with the shortening of a gate length Lg, a Vth is shifted to the OFF side. When an Si3N4 film is deposited, the Vth is also shifted to the OFF side. When the Vth is shifted to the OFF side by the shortening of the gate length Lg, the channel effect is inevitably suppressed, and the uniformity of the Vth becomes excellent.

公开(公告)号：JPS61168269A

公开(公告)日：1986-07-29

申请号：JP800885

申请日：1985-01-19

Applicant: SONY CORP

Inventor： DOSEN MASASHI ,  WADA MASARU

IPC: H01L21/337 ,  H01L29/808

Abstract: PURPOSE:To set the parasitic capacity at the side of a gate region to substantially zero by forming the second conductive type gate region through a hole on the first conductive layer semiconductor layer on a substrate, and forming a gate electrode having a small hole at the gate region. CONSTITUTION:An N-type GaAs layer 2 is epitaxially grown on a semi- insulating GaAs substrate 1, an Si3N4 film 3 is coated thereon, and a hole 3a is then formed. Then, a P-type impurity is thermally diffused in the layer 2 through the hole 3a to form a P -type gate region 4. Then, after a Ti/Pt/Au film is coated on the entire surface, the gate electrode 5 of narrow width is formed in the hole 3. Then, with the electrode 5 and the film 3 as masks the region 4 is sand-etched to form the region 4 to the prescribed width value smaller than the width of the electrode 5. Then, holes 3b, 3c are formed at the prescribed positions of the film 3, and a source electrode 6 and a drain electrode 7 are then coated.

公开(公告)号：JPS61100965A

公开(公告)日：1986-05-19

申请号：JP22239384

申请日：1984-10-23

Applicant: Sony Corp

Inventor： TOGASHI HIROSHI ,  WADA MASARU ,  KATO YOJI ,  WATANABE SEIICHI

IPC: H01L29/739 ,  H01L29/74

CPC classification number: H01L29/74 ,  H01L29/739

Abstract: PURPOSE:To manufacture an integrated circuit by a SCR having excellent high speed properties and other semiconductor elements by applying the operation of a lateral bipolar transistor by using a semi-insulating semiconductor. CONSTITUTION:In m, p, n and p regions in one main surface 11a of a semiconductor layer 11 consisting of GaAs, etc., the holes of carriers from a region 13 are injected to a semi-insulating region under the region 13, a virtual base 20 is formed, the injection of the electrons of majority carriers in a region 12 is demanded, said electrons flow through the region 14 side through the virtual base, and bipolar transistor operation is conducted between the regions 12-14. A virtual base region 21 is also shaped in regions 13, 14 and 15 similarly to obtain a pnp type. The electrons of majority carriers in the region 12 reach the region 15 through virtual base regions 20, 21 in the semi-insulating semiconductor by the operation of the npn type and pnp type bipolar transistors, the holes of carriers from the region 15 reach the region 12 through the inside of the semi-insulating semiconductor, and SCR operation is conducted.

Abstract translation: 目的：通过使用半绝缘半导体施加横向双极晶体管的操作，通过具有优异的高速性能的SCR制造集成电路和其他半导体元件。 构成：在由GaAs等构成的半导体层11的一个主表面11a的m，p，n和p区域中，来自区域13的载流子孔注入区域13的半绝缘区域， 形成虚拟基座20，需要在区域12中注入多数载流子的电子，所述电子通过虚拟基极流过区域14侧，并且在区域12-14之间进行双极晶体管操作。 类似地，虚拟基区21也在区域13,14和15中成形，以获得pnp类型。 区域12中的多数载流子的电子通过npn型和pnp型双极晶体管的操作而到达半绝缘半导体中的虚拟基极区域20,21的区域15，来自区域15的载流子孔到达区域 12通过半绝缘半导体的内部，并进行SCR操作。

公开(公告)号：JPS6174372A

公开(公告)日：1986-04-16

申请号：JP19594184

申请日：1984-09-19

Applicant: Sony Corp

Inventor： WADA MASARU ,  TAKAKUWA HIDEMI

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/10

CPC classification number: H01L29/1066

Abstract: PURPOSE:To control independently the threshold values of two modes by a method wherein an impurity is diffused in a region in the semiconductor substrate, where the FET gate in the mode on the other side of the two modes is formed, in a state that the FET forming part in the mode on one side of the two modes is masked. CONSTITUTION:A channel layer 2 is formed on part of the surface of a semicon ductor substrate 1 and an insulating layer 3 is formed on the substrate 1. After diffusion windows are formed on the layer 3, acceptor (zinc) is diffused in part of the surface of the channel layer 2 and p-type semiconductor regions 4e and 4d are formed. At the time of this diffusion, the depths of the regions 4e and 4d are controlled and the threshold value of the mode of the part of the region 4d is set at the threshold value of the FET in a depletion mode. Moreover, an insulating layer 5 is formed, zinc is further diffused in a part, where the region 4e is already formed, through the diffusion window and the threshold value of the mode of the part of the region 4e is set at the threshold value of the FET in an enhancement mode. After that, gate electrodes 7 and source and drain electrodes 8 and 9 are formed.

Abstract translation: 目的：通过一种方法来独立地控制两种模式的阈值，其中杂质扩散在半导体衬底中的区域中，其中形成两种模式的另一侧的模式中的FET栅极处于 在两种模式的一侧的模式中形成FET的部分被屏蔽。 构成：在半导体基板1的一部分表面上形成沟道层2，在基板1上形成绝缘层3.在层3上形成扩散窗后，受体（锌）部分扩散 形成沟道层2和p型半导体区域4e和4d的表面。 在该扩散时，区域4e和4d的深度被控制，并且区域4d的部分的模式的阈值被设置为处于耗尽模式的FET的阈值。 此外，形成绝缘层5，通过扩散窗将锌进一步扩散到已经形成区域4e的部分中，并且区域4e的部分的模式的阈值被设定为阈值 FET处于增强模式。 之后，形成栅电极7和源极和漏电极8和9。

公开(公告)号：JPS60116172A

公开(公告)日：1985-06-22

申请号：JP22484383

申请日：1983-11-29

Applicant: SONY CORP

Inventor： TAIRA KENICHI ,  WADA MASARU ,  KATOU YOUJI ,  DOUSEN MASASHI

IPC: H01L29/808 ,  H01L21/331 ,  H01L21/337 ,  H01L29/20 ,  H01L29/72 ,  H01L29/73

Abstract: PURPOSE:To perform a bipolar operation by forming the first and second regions in semi-insulating regions, and selectively providing the other third conductive type region on the semiconductor between the both the first and the second regions, thereby applying a forward bias between the third and the first regions, and forming an imaginary base region under the third region. CONSTITUTION:P type impurity is doped in high density on the main surface 10a of a semi-insulating semiconductor 10 to form a semiconductor layer 11, and a base electrode 12 is selectively coated on the layer 11. With the electrode 12 as a mask an N type impurity ions different from the layer 11 are implanted from the main surface side of the semiconductor 10, thereby forming the first and second regions 13, 14 as emitter and collector regions. Then, the layer 11 is selectively etched to set the remaining layer 11 as the third region. Emitter and collector electrodes 15, 16 are coated on the regions 13, 14, respectively. A forward bias potential is applied between the region 13 and the layer 11, an imaginary base region due to the implantation of the majority carrier from the layer 11 is formed in the semiconductor 10 under the layer 11, thereby performing a bipolar transistor operation.

公开(公告)号：JPH1041321A

公开(公告)日：1998-02-13

申请号：JP19714996

申请日：1996-07-26

Applicant: SONY CORP

Inventor： YAMAGATA HIDEO ,  YASUSHIGE HIROAKI ,  WADA MASARU

IPC: H01L29/73 ,  H01L21/205 ,  H01L21/331 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To restrain lowering of apparent impurity concentration in an emitter layer of second conductivity type affected by impurity gas forming one conductivity type which remains inside a chamber when a base layer and an emitter layer are formed continuously by an epitaxial technique. SOLUTION: In a manufacturing method of a bipolar transistor having a process for continuously forming a base layer of first conductivity type on a semiconductor board and an emitter layer of second conductivity type on the base layer by epitaxial technique, impurity gas for forming second conductivity type to remove impurity gas for forming first conductivity type used when a base layer is formed is introduced to epitaxial growth atmosphere after formation S3 of the base layer and before formation S7 of the emitter layer and displacement S4 of gas for displacing the atmosphere by impurity gas for forming second conductivity type.

公开(公告)号：JPH0555498A

公开(公告)日：1993-03-05

申请号：JP23740691

申请日：1991-08-23

Applicant: SONY CORP

Inventor： WADA MASARU

IPC: H01L27/095

Abstract: PURPOSE:To prevent the time delay at gates of JFETs in a DCFL circuit if a source voltage VDD is increased. CONSTITUTION:A DCFL circuit, composed of resistors 3 and 4 and JFETs 1 and 2, is formed between a power source line VDD and a ground line GND. The JFETs 1 and 2 are connected at their gate inputs with voltage drop resistors 5 and 6, respectively. The resistors 5 and 6 serve to decrease the gate voltages if the source voltage VDD rises. This restricts the flow of minority carriers into the gates to prevent the increase in time delay at the gates.

公开(公告)号：JPH0548025A

公开(公告)日：1993-02-26

申请号：JP23248091

申请日：1991-08-21

Applicant: SONY CORP

Inventor： FURUTA TAKESHI ,  WADA MASARU

IPC: H01L27/095 ,  H03K19/0952

Abstract: PURPOSE:To enable a voltage of a high-level side of logic amplitude of an output level when a push-pull buffer is adopted to be increased for securing an operation margin at the next stage. CONSTITUTION:A push-pull buffer consisting of a pair of enhancement-type FETs 3 and 4 is provided between a power supply voltage VDD and a grounding voltage GND and a resistor 1 is provided between an output terminal 8 of the push-pull buffer and the power-supply voltage VDD. When an output level is high, the output terminal 8 is discharged through the resistor 1 and then a high level of a logic amplitude of the output level can be increased to a level of the power supply voltage VDD.

公开(公告)号：JPH01130543A

公开(公告)日：1989-05-23

申请号：JP29035487

申请日：1987-11-17

Applicant: SONY CORP

Inventor： WADA MASARU ,  OKUHORA AKIHIKO

IPC: H01L21/3205

Abstract: PURPOSE:To form a film on a pattern in uniform thickness by a method wherein an etching operation is conducted until an interlayer insulating layer is exposed under the condition in which a flattened film is selectively etched, and then the whole surface is etched so that the interlayer insulating layer is formed into the prescribed thickness. CONSTITUTION:After an insulating layer 12 and a wiring pattern 13 have been formed on a substrate 11, an SiO2 layer 14 having sufficient thickness is formed, and then a flattened film 15 is formed by applying photoresist on the layer 14. The film 15 only is selectively etched until the layer 14 on the pattern 13 is exposed. Then, the layer 14 and the partially left film 15 are etched until the layer 14 on the pattern 13 is formed into the prescribed thickness. The layer 14, which is an interlayer insulating layer, is flattened and the interlayer insulating layer 14 of uniform thickness is formed on patterns 13A and 13B. As a result, the interlayer insulating layer on the pattern can be flattened in the prescribed thickness irrespective of the width of the pattern.

公开(公告)号：JPS61170071A

公开(公告)日：1986-07-31

申请号：JP1033585

申请日：1985-01-23

Applicant: SONY CORP

Inventor： DOSEN MASASHI ,  WADA MASARU

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/80

Abstract: PURPOSE:To prevent the flowing of currents between a channel layer and a gate region by forming a stepped section at the end of a conduction band to a hetero-junction shaped between first and second compound semiconductor layers. CONSTITUTION:An AlxGa1-x As layer 11 having electron affinity smaller than an N-type GaAs layer 3 is formed onto the N-type GaAs layer 3 constituting a channel layer. There is a stepped section DELTAEc=0.3eV (x=0.3) at the end Ec of the conduction band of both semiconductors on a hetero-junction 15 formed by the N-type GaAs layer 3 and the AlxGa1-xAs layer 11. Accordingly, the flowing of electrons into a gate region 8 from the N-type GaAs layer 3 on the operation of a GaAs J-FET is obviated effectively by the stepped section DELTAEc, thus preventing the flowing of currents between the N-type GaAs layer 3 and the gate region 8.