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公开(公告)号：DE69800785D1
公开(公告)日：2001-06-21
申请号：DE69800785
申请日：1998-07-03
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: A detection circuit for access anomalies in microcontroller cell access consists of a central information processor (14), at least one RAM (18) of which part (26) is reserved for the cell, an input/output circuit (20) and a communication bus (22). The circuit incorporates a first detector 28) for all access to the cell (26), a second detector (32, 34) for any instruction giving access to the cell and an alarm signal generator (46) for when any access to the cell is detected outside an instruction containing such access. It also has a means (20) of interrupting the function of the micro-controller when an alarm signal is given.
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公开(公告)号：FR2793904A1
公开(公告)日：2000-11-24
申请号：FR9906499
申请日：1999-05-21
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: Procedure in which a masking current is applied to variations in the current taken by an electronic circuit during a fraction of the total time (ti-tj) but which includes any period where confidential data is being read from a EEPROM memory. An Independent claim is made for an electronic circuit for implementing the above procedure.
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公开(公告)号：DE60322818D1
公开(公告)日：2008-09-25
申请号：DE60322818
申请日：2003-10-16
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , WUIDART LUC
Abstract: The memory cell (1) comprises at least one, in particular two branches (2,3) connected between two terminals (4,5) where the read voltage (Vr) is applied; each branch comprises two stages connected in series, that is a pre-read stage (6,7) each with two switchable resistors (Rg1,Rg2;Rg3,Rg4) connected in parallel, and a programming stage (8,9) containing a programmable resistor (Rp1,Rp2) of polycrystalline silicon, where the programmable resistors terminals (14,15) are accessible to a proper programming circuit to implement an irreversible decrease of each programmable resistance. The decrease (delta)Rp of the value of the programmable resistance (Rp1,Rp2) is predetermined and chosen to be greater than the difference (delta)Rg between two resistances (Rg1,Rg2;Rg3,Rg4) in the pair of each pre-read stage (6,7). The memory cell also comprises interrupters (K10,K11) for isolating the pre-read stages (6,7) from the programming stages (8,9). The programming stages comprise switches (K14,K15) for aplying the programming voltage (Vp) which is higher than the read voltage (Vr) to the terminals of the programmable resistors (Rp1,Rp2). The reading of the cell state is effected in two successive steps in the course of which the switchable resistors (Rg1,Rg2,Rg3,Rg4) of the pre-read stages are alternatingly selected. Each programmable resistor (Rp1,Rp2) is connected to the lower supply voltage terminal, in particular the ground (5) by a transistor (MN1,MN2) connected as a bistable with the transistor of the other branch. The switchable resistors (Rg1,Rg2;Rg3,Rg4) of the two branches (2,3) are simultaneously controlled so that the values of the selected resistances in each branch are inverted. The irreversible decrease (delta) Rp of the programmable resistances is greater than the difference (E) of the nominal values of the programmable resistances in the non-programmed state. In a variant of the memory cell, the terminal of the programmable resistor is the read terminal which is connectable to the first input of an amplifier whose second input is connected to a reference potential which is chosen at a level intermediate between the voltage levels at the read terminal in the two read phases when the programmable resistance is in the non-programmed state. A method (claimed) for reading the memory cell (claimed) consists in effecting two successive read steps in the course of which the switchable resistances of the pre-read stage are selected.
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公开(公告)号：DE60220975T2
公开(公告)日：2008-03-13
申请号：DE60220975
申请日：2002-09-03
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , WUIDART LUC , BARDOUILLET MICHEL , BALLTHAZAR PIERRE
IPC: G01K7/00 , G06K19/073 , G06F12/14 , G06F13/42 , G06F21/06 , H01L21/822 , H01L27/04
Abstract: Method for detection of variations of an evironmental parameter (V,T) in an integrated circuit (1): (a) evaluate a propagation delay for retarding parts (21) sensitive to variations parameters environment, and; compare the delay current with respect to a reference value (REF). The measured delay current is compared to two predetermined minimum and maximum levels or a unique reference value defining a authorized operating range for the integrated circuit. The value from programmable retarder is determined as a function of the difference between the current value and reference value. The range of possible variation being predetermined.
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公开(公告)号：DE60113721T2
公开(公告)日：2006-06-29
申请号：DE60113721
申请日：2001-12-19
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: Operation of a logic circuit for performing a desired logic function is scrambled. Logic gates and/or transistors are provided in the logic circuit so that the logic function is performed in at least two different ways. The way in which the logic function is performed is determined by the value of a function selection signal applied to the logic circuit. The function selection signal is random and is applied to the logic circuit, and the function selection signal is refreshed at determined instants for scrambling operation of the logic circuit. For identical data applied at the input of the logic circuit and for different values of the function selection signal, the polarities of certain internal nodes of the logic circuit and/or the current consumption of the logic circuit are not identical.
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Patent Agency Ranking
公开(公告)号：DE60109181D1
公开(公告)日：2005-04-07
申请号：DE60109181
申请日：2001-09-10
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
IPC: G06F1/00 , G06F21/55 , H01L23/58 , G06K19/073
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公开(公告)号：DE69730064D1
公开(公告)日：2004-09-09
申请号：DE69730064
申请日：1997-02-19
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: An integrated circuit (1) receives an external clock signal (CK-ext) and in addition has a random generator (2) which produces a random clock signal (CK-al). The external and random clock signals are applied to a switching circuit (3). The switching circuit (3) is controlled by signals (K) from a group of circuits (5) including memories, data and processors and operates to select either the external or random clock signal for entry to the internal clock signal generator (4). The clock signal selection is such that the external signal is only used for external synchronisation.
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公开(公告)号：DE60103397D1
公开(公告)日：2004-06-24
申请号：DE60103397
申请日：2001-05-28
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
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公开(公告)号：FR2813972B1
公开(公告)日：2003-12-12
申请号：FR0011696
申请日：2000-09-14
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
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公开(公告)号：FR2793904B1
公开(公告)日：2001-07-27
申请号：FR9906499
申请日：1999-05-21
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART SYLVIE
Abstract: The invention proposes a method of managing an electronic circuit of the type comprising a memory (EEPROM) for the storage of confidential information, the method comprising masking variations of the electrical current (I) consumed by the electronic circuit, during a fraction of the time only (t i -t j ), at least during the portion(s) of time during which an instruction bearing on confidential data is executed, and notably an instruction for reading out from the memory (EEPROM).
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