公开(公告)号：JP2008065843A

公开(公告)日：2008-03-21

申请号：JP2007259733

申请日：2007-10-03

Applicant: St Microelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： WUIDART SYLVIE

IPC: G06F1/04 ,  G06K19/07 ,  G06F1/06 ,  G06F1/08 ,  G06F21/06 ,  G06K17/00 ,  G06K19/073

CPC classification number: G06K19/073 ,  G06F1/08 ,  G06K19/07363

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit capable of using an external clock signal or random clock signal as an internal synchronizing signal. SOLUTION: The integrated circuit (1) which receives the external clock signal (CK-ext) is controlled in clocking internally and the random clock signal (CK-al) which is generated internally is used additionally. With a binary switching command K corresponding to an instruction to be executed, one of those clock signals (CK-ext and CK-al) is used as a base for clock generation and an internal clock signal (CK-in) is obtained according to the one of them. The random clock signal (CK-al) is preferably used as the base for operation for processing at least secret data. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够使用外部时钟信号或随机时钟信号作为内部同步信号的集成电路。

解决方案：接收外部时钟信号（CK-ext）的集成电路（1）在内部进行时钟控制，另外使用内部生成的随机时钟信号（CK-a1）。 使用与要执行的指令对应的二进制切换命令K，将这些时钟信号（CK-ext和CK-a1）中的一个用作时钟产生的基准，并且根据以下情况获得内部时钟信号（CK-in） 其中之一。 随机时钟信号（CK-a1）优选地用作用于至少处理秘密数据的操作的基础。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003243525A

公开(公告)日：2003-08-29

申请号：JP2002257486

申请日：2002-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE ,  WUIDART LUC ,  BARDOUILLET MICHEL ,  BALTHAZAR PIERRE

IPC: G01K7/00 ,  G06F12/14 ,  G06F13/42 ,  G06F21/06 ,  G06K19/073 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for detecting the variation of at least one environmental parameter of an integrated circuit. SOLUTION: A propagation delay of an edge in a delay element sensitive to the variation of the environmental parameter is measured to compare a present or a measured delay with at least one reference value. COPYRIGHT: (C)2003,JPO

公开(公告)号：DE60128646T2

公开(公告)日：2008-01-31

申请号：DE60128646

申请日：2001-11-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE ,  WUIDART SYLVIE

IPC: G06F12/14 ,  G06F21/55

Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.

公开(公告)号：DE60109181T2

公开(公告)日：2005-12-29

申请号：DE60109181

申请日：2001-09-10

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE

IPC: G06F1/00 ,  G06F21/55 ,  H01L23/58 ,  G06K19/073

公开(公告)号：FR2819070A1

公开(公告)日：2002-07-05

申请号：FR0017261

申请日：2000-12-28

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE ,  WUIDART SYLVIE

IPC: G06F21/55 ,  G06F12/14 ,  G06K19/073

Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.

公开(公告)号：FR2818845A1

公开(公告)日：2002-06-28

申请号：FR0016747

申请日：2000-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE

IPC: G06F1/00 ,  G06F21/79 ,  G06F21/85 ,  H04L9/18 ,  G06F12/14

公开(公告)号：FR2813972A1

公开(公告)日：2002-03-15

申请号：FR0011696

申请日：2000-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE

IPC: G06F1/00 ,  G06F21/55 ,  H01L23/58 ,  G06K19/073 ,  H04L9/06 ,  H04L9/32

Abstract: The invention concerns a method for jamming the power consumption of an integrated circuit (10), at least during the execution by the integrated circuit of a confidential operation (T2) which consists in scanning the confidential data (Ks) stored in the integrated circuit and/or calculating a cryptographic code. The invention is characterised in that it consists in activating a charge pump (PMP) so as to generate on the power supply line of the integrated circuit power consumption fluctuations (Icc2) of sufficient intensity to mask the variations on power consumption related to the execution of the confidential operation.

公开(公告)号：DE602007002650D1

公开(公告)日：2009-11-19

申请号：DE602007002650

申请日：2007-02-09

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE

IPC: G06F21/55

Abstract: The method involves conditioning a result of a calculation at states of verification bits (Bi) respectively allocated to registers. The calculation result is set at an active state when the corresponding register is accessed during execution of the calculation independent of content of the register. The result is multiplied by a product (B) of the verification bits before the result is provided by an electronic circuit. An independent claim is also included for an electronic circuit comprising a processing unit.

公开(公告)号：DE60220975D1

公开(公告)日：2007-08-16

申请号：DE60220975

申请日：2002-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE ,  WUIDART LUC ,  BARDOUILLET MICHEL ,  BALLTHAZAR PIERRE

IPC: G01K7/00 ,  G06K19/073 ,  G06F12/14 ,  G06F13/42 ,  G06F21/06 ,  H01L21/822 ,  H01L27/04

Abstract: Method for detection of variations of an evironmental parameter (V,T) in an integrated circuit (1): (a) evaluate a propagation delay for retarding parts (21) sensitive to variations parameters environment, and; compare the delay current with respect to a reference value (REF). The measured delay current is compared to two predetermined minimum and maximum levels or a unique reference value defining a authorized operating range for the integrated circuit. The value from programmable retarder is determined as a function of the difference between the current value and reference value. The range of possible variation being predetermined.

公开(公告)号：DE69730064T2

公开(公告)日：2005-07-14

申请号：DE69730064

申请日：1997-02-19

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE

IPC: G06K19/07 ,  G06F1/04 ,  G06F1/08 ,  G06K17/00 ,  G06K19/073 ,  G06F1/00

Abstract: An integrated circuit (1) receives an external clock signal (CK-ext) and in addition has a random generator (2) which produces a random clock signal (CK-al). The external and random clock signals are applied to a switching circuit (3). The switching circuit (3) is controlled by signals (K) from a group of circuits (5) including memories, data and processors and operates to select either the external or random clock signal for entry to the internal clock signal generator (4). The clock signal selection is such that the external signal is only used for external synchronisation.