中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

71 records (took 0.029 seconds)

    SYSTEM AND METHOD FOR SELECTING A CLOCK
    31.
    发明申请
    SYSTEM AND METHOD FOR SELECTING A CLOCK 审中-公开

    公开(公告)号：US20200278393A1

    公开(公告)日：2020-09-03

    申请号：US16791020

    申请日：2020-02-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mirko Dondini ,  Daniele Mangano ,  Salvatore Pisasale

    IPC: G01R31/3185 ,  G01R31/319 ,  G01R29/027 ,  G06F1/08 ,  G06F1/12 ,  G06F13/24

    Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

    Method and system for performing division/multiplication operations in digital processors, corresponding device and computer program product
    32.
    发明授权
    Method and system for performing division/multiplication operations in digital processors, corresponding device and computer program product 有权

    公开(公告)号：US10108396B2

    公开(公告)日：2018-10-23

    申请号：US14313273

    申请日：2014-06-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano

    IPC: G06F5/01 ,  G06F7/52 ,  G06F7/523 ,  G06F7/535

    Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

    Debug system, and related integrated circuit and method
    37.
    发明授权
    Debug system, and related integrated circuit and method 有权
    调试系统及相关集成电路及方法

    公开(公告)号：US09389979B2

    公开(公告)日：2016-07-12

    申请号：US14038501

    申请日：2013-09-26

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

    IPC: G06F11/00 ,  G06F11/27 ,  G06F11/36 ,  G06F11/22

    CPC classification number: G06F11/27 ,  G06F11/2236 ,  G06F11/3648

    Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.

    Abstract translation: 系统包括处理器和通过互连网络连接的多个电路，其中与每个电路相关联的是相应的通信接口，被配置为在相应电路和互连网络之间交换数据。 特别地，调试单元与每个通信接口相关联。 每个调试单元可配置为数据插入点，其中调试单元通过相应的通信接口将数据发送到互连网络，或者每个调试单元可配置为数据接收点，其中调试单元通过 来自互连网络的相应通信接口的装置。

    COMMUNICATION INTERFACE FOR INTERFACING A TRANSMISSION CIRCUIT WITH AN INTERCONNECTION NETWORK, AND CORRESPONDING SYSTEM AND INTEGRATED CIRCUIT
    38.
    发明申请
    COMMUNICATION INTERFACE FOR INTERFACING A TRANSMISSION CIRCUIT WITH AN INTERCONNECTION NETWORK, AND CORRESPONDING SYSTEM AND INTEGRATED CIRCUIT 有权
    用于连接具有互连网络的传输电路的通信接口以及相关系统和集成电路

    公开(公告)号：US20150370734A1

    公开(公告)日：2015-12-24

    申请号：US14841522

    申请日：2015-08-31

    Applicant: STMicroelectronics S.R.L.

    Inventor： Daniele Mangano ,  Mirko Dondini ,  Salvatore Pisasale

    IPC: G06F13/28 ,  G06F3/06

    CPC classification number: G06F13/28 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/067 ,  G06F13/4059 ,  G06F2213/0038

    Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.

    Abstract translation: 通信接口将传输电路与互连网络耦合。 发送电路请求发送预定量的数据。 通信接口从发送电路接收数据段，将数据段存储在存储器中，并且验证存储器是否包含预定量的数据。 在存储器包含预定量的数据的情况下，通信接口开始存储在存储器中的数据的发送。 或者，在存储器包含小于预定数据量的数据量的情况下，通信接口确定从上述发送电路接收到从发送请求或第一基准开始经过的时间的参数， 并验证所经过的时间是否超过时间阈值。 在经过时间超过时间阈值的情况下，通信接口开始存储在存储器中的数据的发送。

    COMMUNICATION SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD
    39.
    发明申请
    COMMUNICATION SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD 有权
    通信系统和相应的集成电路和方法

    公开(公告)号：US20150207581A1

    公开(公告)日：2015-07-23

    申请号：US14604439

    申请日：2015-01-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Salvatore Pisasale

    IPC: H04J3/06 ,  H04L7/04 ,  H04L12/26

    CPC classification number: H04L43/0858 ,  G06F1/04 ,  G06F13/4291 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/005 ,  H04L7/10

    Abstract: A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct. The system is further configured to use, during normal operation, the clock signal selected during the calibration phase for transmission of data.

    Abstract translation: 用于将发射电路与接收电路接口的通信系统包括用于从发射电路接收数据的传输接口，并响应于传输时钟信号发射通过至少一条数据线接收的数据。 通信系统还包括：接收接口，被配置为响应于接收时钟信号接收数据，并将接收到的数据发送到接收电路。 特别地，该系统被配置为产生具有相同频率但是相对于彼此相移的多个时钟信号。 此外，在校准阶段期间，系统被配置为通过经由传输接口选择用于传输测试信号的时钟信号中的至少一个来选择传输时钟信号或接收时钟信号中的一个时钟信号，并且验证 通过接收接口接收到的测试信号是正确的。 该系统还被配置为在正常操作期间使用在校准阶段期间选​​择的用于传输数据的时钟信号。

    Power supply circuit, corresponding device and method
    40.
    发明授权
    Power supply circuit, corresponding device and method 有权

    公开(公告)号：US11906994B2

    公开(公告)日：2024-02-20

    申请号：US17836524

    申请日：2022-06-09

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

    Inventor： Daniele Mangano ,  Andrei Tudose ,  Francesco Clerici ,  Pasquale Butta'

    IPC: G06F1/00 ,  G05F1/46 ,  G06F1/3296

    CPC classification number: G05F1/468 ,  G06F1/3296

    Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.

Patent Agency Ranking