公开(公告)号：EP0887933A1

公开(公告)日：1998-12-30

申请号：EP97830298.2

申请日：1997-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

IPC: H03K17/06

CPC classification number: H03K17/063 ,  H03K2217/0018

Abstract: A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance, via a bootstrap capacitor (Cp) charged by a diode at the supply voltage (Vs) of the circuit, by an inverter (IO1) driven by a logic control circuit in function of a Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase wherein the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, uses a first zener diode (Z1) to charge the bootstrap (Cp) and the source of the (LD) transistor is connected to the supply node (Vs) through a second zener diode (Z2).

Abstract translation: 一种用于通过用作源极跟随器的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，其通过经由自举电容器（Cp）的电容器（Cp）来模拟电容器的高电压充电二极管 通过由低栅极驱动信号的功能的逻辑控制电路驱动的反相器（IO1）和在阶段期间有效的第二逻辑信号（UVLOb）的电路的电源电压（Vs）处的二极管， 电源电压（Vs）低于集成电路的最小接通电压，使用第一齐纳二极管（Z1）对自举（Cp）充电，并且（LD）晶体管的源极连接到电源节点 Vs）通过第二齐纳二极管（Z2）。

公开(公告)号：EP0887932A1

公开(公告)日：1998-12-30

申请号：EP97830297.4

申请日：1997-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Genova, Angelo ,  Tarantola, Mario ,  Cantone, Giuseppe ,  Gariboldi, Roberto

IPC: H03K17/06

CPC classification number: H03K17/063 ,  H03K2217/0018

Abstract: A circuit for charging a capacitance (C) by mens of an LDMOS (LD) integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance and comprising a circuital device to avert the switch-on parasitic PNP transistors of the LDMOS structure during transient states, composed of a number n of junctions (d1, D2, .. , Dn) directly biased between a source node (S) and a body node (VB) of the LDMOS transistor, at least a current generator (I), referred to the potential of a ground node of the circuit, at least a switch (SW1) between said source node (S) and the first junction (D1) of said chain of directly biased junctions and a limiting resistance (R1) connected between said body node and said current generator (I) referred to ground in which the (SW1) switch is open during a charging phase of the capacitance (C) and is closed when the charging voltage of the capacitance goes over a preestablished threshold by a control signal, further comprises

switching means (Sd1, Sd2, Sd3, Sd4) controlled by a logic signal (UVLO), active during the phase in which the supply voltage (Vs) of the integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit, for charging said body node (VB) with a current whose maximum value is limited to a preestablished value.

Abstract translation: 一种用于以模拟高电压充电二极管的方式控制的LDMOS（LD）集成晶体管的电容（C）进行充电的电路，并且包括电路装置以反转LDMOS的接通的寄生PNP晶体管 由在直接偏置在LDMOS晶体管的源极节点（S）和体节点（VB）之间的n个结（d1，D2，...，Dn）组成的至少一个电流发生器（I ）指的是电路的接地节点的电位，至少在所述源极节点（S）和所述直接偏置接合链的第一结（D1）之间的开关（SW1）和连接的限制电阻（R1） 在所述体节点和所述电流发生器（I）之间称为接地，其中（SW1）开关在电容（C）的充电阶段期间断开，并且当电容的充电电压超过预先建立的阈值时闭合 控制信号还包括切换 由逻辑信号（UVLO）控制的装置（Sd1，Sd2，Sd3，Sd4）在集成电路的电源电压（Vs）低于同一集成电路的最小接通电压的相位中有效， 用于用最大值被限制为预定值的电流对所述身体节点（VB）进行充电。

公开(公告)号：EP0687066B1

公开(公告)日：1999-10-06

申请号：EP94830284.9

申请日：1994-06-10

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bontempo, Gregorio ,  Pulvirenti, Francesco ,  Colletti, Paolo ,  Gariboldi, Roberto

IPC: H03K17/082

CPC classification number: H03K17/284 ,  H03K17/0822

公开(公告)号：EP0782235A1

公开(公告)日：1997-07-02

申请号：EP95830550.0

申请日：1995-12-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Pulvirenti, Francesco ,  Bontempo, Gregorio ,  Gariboldi, Roberto

IPC: H02H1/00 ,  H03K17/082

CPC classification number: H03K17/0822 ,  H03K2017/0806 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.
The method of this invention provides for:

the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; and
the utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

The power transistor (PW) is turned on again, and the current limiting circuit (4) inhibited, by the following steps:

a) generating an electric signal which is substantially proportional to the voltage appearing at the output terminal (OUT) of the actuator;
b) driving the control terminal (G) of the power transistor (PW) by means of said electric signal, and causing said transistor to conduct, while simultaneously disabling the current limiting circuit (4) when the output voltage exceeds a predetermined threshold; and
c) allowing the transient energy to be dissipated to the power transistor (PW).

Abstract translation: 本发明的目的在于提供一种用于保护功率执行器的输出级以防止浪涌型电压瞬变的方法和电路。 特别地，它提供了针对包含在执行器的输出级中的功率晶体管的国际标准IEC 801-5所述类型的电压浪涌瞬变的保护。 本发明的方法提供：功率晶体管（PW）本征二极管（DP）用于在正瞬变期间将瞬态能量倾倒到一个供电发生器端子; 以及在负瞬态期间将功率晶体管（PW）恢复特性应用于导通状态以将能量倾倒在其中，同时抑制电流限制功能。 功率晶体管（PW）再次导通，并且限流电路（4）通过以下步骤来禁止：a）产生基本上与致动器的输出端（OUT）处出现的电压成比例的电信号 ; b）通过所述电信号驱动功率晶体管（PW）的控制端（G），并使所述晶体管导通，同时当所述输出电压超过预定阈值时禁止所述限流电路（4）; 以及c）允许瞬态能量被耗散到功率晶体管（PW）。

公开(公告)号：EP0735677A1

公开(公告)日：1996-10-02

申请号：EP95830123.6

申请日：1995-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Pulvirenti, Francesco ,  Ursino, Riccardo ,  Gariboldi, Roberto

IPC: H03K3/011 ,  H03K3/0231

CPC classification number: H03K3/011 ,  H03K3/0231 ,  H03K3/354

Abstract: The oscillating circuit in accordance with the present invention comprises a capacitor C, a charge circuitry CCA and a control circuitry CCO. The charge circuitry CCA includes a first GEN1 and a second GEN2 current generators having respectively a first and a second current values and opposite directions and switching means SW1,SW2 designed to couple alternatively the generators GEN1,GEN2 to the capacitor C. The control circuitry CCO has a voltage input coupled to the capacitor C and an output coupled to control inputs of the switching means SW1,SW2 and includes a comparator with hysteresis having a lower threshold and an upper threshold.
If for the difference between the upper threshold and the lower threshold a value is chosen essentially proportional to the ratio of the product to the sum of the two current values the oscillation frequency and the duty cycle depend neither on the supply voltage nor the temperature nor the process.

Abstract translation: 根据本发明的振荡电路包括电容器C，充电电路CCA和控制电路CCO。 充电电路CCA包括分别具有第一和第二电流值和相反方向的第一GEN1和第二GEN2电流发生器，以及设计成将发电机GEN1，GEN2交替耦合到电容器C的开关装置SW1，SW2。控制电路CCO 具有耦合到电容器C的电压输入和耦合到开关装置SW1，SW2的控制输入的输出，并且包括具有较低阈值和较高阈值的滞后的比较器。 如果对于上限阈值和下限阈值之间的差异，则选择一个值基本上与产品与两个电流值之和的比例成比例，振荡频率和占空比既不依赖于电源电压也不依赖于温度， 处理。

公开(公告)号：EP0687066A1

公开(公告)日：1995-12-13

申请号：EP94830284.9

申请日：1994-06-10

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bontempo, Gregorio ,  Pulvirenti, Francesco ,  Colletti, Paolo ,  Gariboldi, Roberto

IPC: H03K17/082

CPC classification number: H03K17/284 ,  H03K17/0822

Abstract: The invention relates to a non-dissipative device for protecting against overloading an integrated circuit having multiple independent channels, being of the type which comprises an input terminal (IN) and an output terminal (OUT) having an integrated switch (1) connected therebetween which consists of a first or input portion (2), a logic gate (PL1) with two inputs (I3,I4) a second or control portion (3), and a third or output portion (4), all in series with one another. The device further comprises a circuit (A) for generating the on- and off-times (Ton,Toff) of the integrated switch (1) connected between an output (O4) of the third portion (4) and an input terminal (I4) of said logic gate (PL1).

Abstract translation: 本发明涉及一种非消散装置，用于防止具有多个独立通道的集成电路的过载，该集成电路具有包括输入端（IN）和输出端（OUT）的类型，该输出端（IN）和输出端（OUT）之间连接有集成开关（1） 由第一或输入部分（2），具有两个输入（I3，I4），第二或控制部分（3）的逻辑门（PL1），以及彼此串联的第三或输出部分（4） 。 该装置还包括用于产生连接在第三部分（4）的输出（O4）和输入端（I4）之间的集成开关（1）的开和关时间（Ton，Toff）的电路（A） ）的逻辑门（PL1）。

公开(公告)号：EP0810504A1

公开(公告)日：1997-12-03

申请号：EP96830312.3

申请日：1996-05-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ursino, Riccardo ,  Gariboldi, Roberto

IPC: G05F1/00 ,  G05F1/575

CPC classification number: G05F1/575

Abstract: The invention relates to a voltage regulator connected between first (VS) and second (GND) voltage references and having an output terminal (O1) for delivering a regulated output voltage (Vout), which voltage regulator comprises at least one voltage divider (11), connected between the output terminal (O1) and the second voltage reference (GND), and a serial output element (18) connected between the output terminal (O1) and the first voltage reference (VS), the voltage divider (11) being connected to the serial output element (18) by a first conduction path which includes at least one error amplifier (EA) of the regulated output voltage (Vout) whose output is connected to at least one driver (DR) for turning off the serial output element (18), the voltage regulator comprising, between the voltage divider (11) and the serial output element (18), at least a second conduction path for turning off the serial output element (18) according to the value of the regulated output voltage (Vout), in advance of the action of the first conduction path.
The invention also concerns a method of turning off a serial output element (18) as a regulated output voltage (Vout) from a voltage regulator (10) changes.

Abstract translation: 本发明涉及连接第一（VS）和第二（GND）电压基准并且具有输出端（O1）之间用于传递经调节的输出电压（Vout）其中电压调节器包括至少一个分压器的电压调节器（11） ，连接在输出端子（01）和所述第二电压基准（GND），和连接在输出端（O1）和第一参考电压（VS）之间的串行输出元件（18）之间，所述分压器（11）是 通过其中包括一个第一导电通路连接到所述串行输出元件（18）至少一个误差放大器中的调节的输出电压的（EA）（VOUT）的输出连接到至少一个驱动器（DR）用于关断串行输出 元件（18），电压调节器包括：在所述分压器（11）和串行输出元件（18）之间，至少用于关断串行输出元件（18）雅丁到经调节的输出的值的第二导电路径 电压（Vout）， 预先在第一导电通路的作用。因此，本发明涉及关闭串行输出元件（18），如从电压调节器（10）的变化的调节的输出电压（Vout）的方法。