Abstract:
Integrated device (202) for use in a monostable circuit (200), the integrated device (202) having a programming terminal (103) able to be linked to external resistive means (Rext) so as to programme the duration of a non-stable state of the circuit (200) and comprising a comparator (120) having a first (+) and a second (-) input terminal and an output terminal for generating an output signal (Vout) of the circuit (200), capacitive means (C) linked to the first input terminal (+) of the comparator (120) so as to apply thereto a voltage (Vc) correlated with the voltage on the capacitive means (C), control means (SW,115) linked to the first input terminal (+) of the comparator (120) so as to switch the circuit (200) to the non-stable state, and means (M1, M2) for sending a current (Iref1) which passes through the resistive means (Rext) to the capacitive means (C), in which the programming terminal (103) is linked to the second input terminal (-) of the comparator (120) so as to apply thereto a voltage (Vref1) correlated with the voltage on the resistive means (Rext).
Abstract:
A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap (Cp) capacitor charged by a diode (D1) connected to the supply node (Vs) of the circuit, by an (IO1) inverter driven by a logic control circuit in function of a first Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase where the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, comprises further a second inverter (M1, M2), functionally referred to the charging node of said bootstrap (Cp) capacitor and to the voltage of the output node (A) of said inverter (IO1) and having an input coupled to said second logic signal (UVLOb) and an output coupled to the gate node of said LDMOS transistor (LD), for preventing accidental undue switch-on of the LDMOS transistor.
Abstract:
A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.
Abstract:
The present invention relates to a current (I) control method for drive systems of multi-phase brushless motors, in particular at phase switching, wherein the motor coils (1,2,3) led to a common node (D) are driven by applying a respective drive voltage to the free end (A,B,C) of each coil (1,2,3) via corresponding power stages (4,5,6). The method comprises switching the current flow from one phase (1-2) to the next (1-3) in the direction of rotation of the motor at the phase switch, thereby forcing the unaffected one (2) of said coils by the phase switch into a state of high impedance. Advantageously, the decreasing rate of the current (I2) in the coil (2) unaffected by the phase switch can be twice as high as the decreasing rate of the current (I1) in the phase being switched from.
Abstract:
A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.
Abstract:
An integrated device (105) for a switching system (100) comprises control means (110) for generating at least one switching control signal (Sh), reference means (120) for generating at least one reference quantity (Qref), means (110) for using the reference quantity (Qref), means (130) for storing the reference quantity (Qref), switch means (122) which, in a first operative condition, connect the reference means (120) to the using means (110) and to the storage means (130) in order to apply the reference quantity (Qref) thereto and, in a second operative condition, disconnect the reference means (120) from the using means (110) and connect the storage means (130) to the using means (110) in order to apply the stored reference quantity thereto, and filtering means (135) for keeping the switch means (122) in the second operative condition for a filtering period (Tf) in accordance with the switching of the control signal (Sh).