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    Multichannel transceiver of digital signals over power lines
    1.
    发明公开
    Multichannel transceiver of digital signals over power lines 有权
    Mehrkanalsender /empfängereines digitalen信号überStromversorgungsleitungen

    公开(公告)号：EP1096695A1

    公开(公告)日：2001-05-02

    申请号：EP99830680.7

    申请日：1999-10-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cappelletti, Roberto ,  Cantone, Giuseppe

    IPC: H04B3/54

    CPC classification number: H04B3/54 ,  H04B2203/5408 ,  H04B2203/542 ,  H04B2203/5437 ,  H04B2203/5458 ,  H04B2203/5483 ,  H04B2203/5491

    Abstract: A data transceiving station of digital data frames comprising a digital modem (MODEM) coupled to a transmission line, a microprocessor (µP) receiving demodulated data from said modem according to a Packet Mode or a Bit Mode transmission through an interface circuit (SERIAL_INTERFACE) that switches from a Packet Mode to a Bit Mode transmission and/or viceversa during transfer of a data frame to said microprocessor conjugating the superior speed of a Packet Mode transfer with the unlimited compatibility of a Bit Mode transfer.

    Abstract translation: 数字数据帧的数据收发站包括耦合到传输线的数字调制解调器（MODEM），微处理器（mu P）根据分组模式或通过接口电路（SERIAL_INTERFACE）的位模式传输从所述调制解调器接收解调数据， 在将数据帧传输到所述微处理器时，从分组模式切换到比特模式传输和/或反转，所述微处理器将分组模式传输的优越速度与位模式传输的无限兼容性相结合。

    Level control of the signal produced by a transceiver coupled to a power distribution line
    4.
    发明公开
    Level control of the signal produced by a transceiver coupled to a power distribution line 有权
    这是由信号接收器感，其被连接到电力线产生的水平调节

    公开(公告)号：EP1089453A1

    公开(公告)日：2001-04-04

    申请号：EP99830618.7

    申请日：1999-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cantone, Giuseppe ,  Cappelletti, Roberto

    IPC: H04B3/54 ,  H04B3/56

    CPC classification number: H04B3/56 ,  H04B3/54 ,  H04B2203/5425 ,  H04B2203/5483 ,  H04B2203/5495 ,  Y10T307/422

    Abstract: The level of the signal output by a transceiver of digital information coupled to a power distribution line during a transmission phase is regulated by comparing the current level (Iref) of said output signal with a pre-established minimum threshold (IL) and a pre-established maximum threshold (IH); reducing the current level (Iref) when said maximum threshold (IH) is exceeded by reducing the gain; and passing to a voltage mode control of said output signal when the current level (Iref) of the output signal becomes lower than said minimum threshold (IL).
    The architecture of a coupling interface implementing the above method is illustrated.

    Abstract translation: 通过的过程中的传输相位耦合到配电线的数字信息的收发器输出的信号的电平是由所述输出信号的电流电平（IREF）与预先建立的最小阈值（IL）和预调节比较 建立的最大阈值（1H）; 降低电流电平（IREF）当通过降低增益超过所述最大阈值（1H）; 并传递到所述输出信号的电压模式控制，当输出信号的电流电平（IREF）变为大于所述最小阈值（IL）下。 一个耦合接口实现上述方法的结构中示出。

    Integrated device for use in a monostable circuit
    5.
    发明公开
    Integrated device for use in a monostable circuit 失效
    在einer monostabilen Schaltung verwendbare integrierte Vorrichtung

    公开(公告)号：EP0909030A1

    公开(公告)日：1999-04-14

    申请号：EP97830506.8

    申请日：1997-10-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Genova, Angelo ,  Gariboldi, Roberto ,  Cantone, Giuseppe

    IPC: H03K3/0232 ,  H03K3/355

    CPC classification number: H03K3/011 ,  H03K3/0232 ,  H03K3/355

    Abstract: Integrated device (202) for use in a monostable circuit (200), the integrated device (202) having a programming terminal (103) able to be linked to external resistive means (Rext) so as to programme the duration of a non-stable state of the circuit (200) and comprising a comparator (120) having a first (+) and a second (-) input terminal and an output terminal for generating an output signal (Vout) of the circuit (200), capacitive means (C) linked to the first input terminal (+) of the comparator (120) so as to apply thereto a voltage (Vc) correlated with the voltage on the capacitive means (C), control means (SW,115) linked to the first input terminal (+) of the comparator (120) so as to switch the circuit (200) to the non-stable state, and means (M1, M2) for sending a current (Iref1) which passes through the resistive means (Rext) to the capacitive means (C), in which the programming terminal (103) is linked to the second input terminal (-) of the comparator (120) so as to apply thereto a voltage (Vref1) correlated with the voltage on the resistive means (Rext).

    Abstract translation: 用于单稳态电路（200）的集成器件（202），该集成器件（202）具有能够连接到外部电阻器件（Rext）的编程端子（103），以便编程不稳定的持续时间 电路（200）的状态，并且包括具有第一（+）和第二（ - ）输入端子的比较器（120）和用于产生电路（200）的输出信号（Vout）的输出端子，电容装置 C）连接到比较器（120）的第一输入端（+），以便向其施加与电容装置（C）上的电压相关的电压（Vc）;与第一输入端连接的控制装置（SW，115） （120）的输入端（+），将电路（200）切换到非稳定状态;以及用于发送通过电阻装置（Rext）的电流（Iref1）的装置（M1，M2） 到电容装置（C），其中编程端子（103）连接到比较器（120）的第二输入端子（ - ），以便施加 到与电阻装置（Rext）上的电压相关的电压（Vref1）。

    Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor
    6.
    发明公开
    Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor 失效
    Schutzschaltung zur Steuerung der Gatterspannung eines Hochspannungs-LDMOS晶体管

    公开(公告)号：EP0887931A1

    公开(公告)日：1998-12-30

    申请号：EP97830296.6

    申请日：1997-06-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tarantola, Mario ,  Cantone, Giuseppe ,  Genova, Angelo ,  Gariboldi, Roberto

    IPC: H03K17/06

    CPC classification number: H03K17/08122 ,  H03K17/063

    Abstract: A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap (Cp) capacitor charged by a diode (D1) connected to the supply node (Vs) of the circuit, by an (IO1) inverter driven by a logic control circuit in function of a first Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase where the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, comprises further a second inverter (M1, M2), functionally referred to the charging node of said bootstrap (Cp) capacitor and to the voltage of the output node (A) of said inverter (IO1) and having an input coupled to said second logic signal (UVLOb) and an output coupled to the gate node of said LDMOS transistor (LD), for preventing accidental undue switch-on of the LDMOS transistor.

    Abstract translation: 一种用于通过用作源极跟随器级的LDMOS集成晶体管（LD）对电容（C）进行充电的电路，以通过经由自举（Cp）电容器充电的自举（Cp）电容器模拟电容的高电压充电二极管的方式被控制 和由第一低栅极驱动信号的逻辑控制电路驱动的（IO1）反相器和第二逻辑信号（UVLOb）连接的电路的供电节点（Vs）的二极管（D1） 在电源电压（Vs）低于集成电路的最小接通电压的阶段中，还包括在功能上称为所述自举（Cp）电容器的充电节点的第二反相器（M1，M2），并且 所述反相器（IO1）的输出节点（A）的电压和耦合到所述第二逻辑信号（UVLOb）的输入端和耦合到所述LDMOS晶体管（LD）的栅极节点的输出端，用于防止意外不适当的开关 - 在LDMOS晶体管上。

    An integrated device for switching systems with filtered reference quantities
    8.
    发明公开
    An integrated device for switching systems with filtered reference quantities 失效
    Integrierte AnordnungfürSchaltsysteme mit gefiltertenBezugsgrössen

    公开(公告)号：EP0896268A1

    公开(公告)日：1999-02-10

    申请号：EP97830415.2

    申请日：1997-08-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Genova, Angelo ,  Cantone, Giuseppe ,  Gariboldi, Roberto

    IPC: G05F1/00 ,  G05F1/575 ,  H03K17/16

    CPC classification number: H03K17/162 ,  G05F3/262

    Abstract: An integrated device (105) for a switching system (100) comprises control means (110) for generating at least one switching control signal (Sh), reference means (120) for generating at least one reference quantity (Qref), means (110) for using the reference quantity (Qref), means (130) for storing the reference quantity (Qref), switch means (122) which, in a first operative condition, connect the reference means (120) to the using means (110) and to the storage means (130) in order to apply the reference quantity (Qref) thereto and, in a second operative condition, disconnect the reference means (120) from the using means (110) and connect the storage means (130) to the using means (110) in order to apply the stored reference quantity thereto, and filtering means (135) for keeping the switch means (122) in the second operative condition for a filtering period (Tf) in accordance with the switching of the control signal (Sh).

    Abstract translation: 一种用于切换系统（100）的集成设备（105）包括用于产生至少一个切换控制信号（Sh）的控制装置（110），用于产生至少一个参考数量（Qref）的参考装置（120） ），用于存储参考数量（Qref）的装置（130），用于存储参考数量（Qref）的装置（130），在第一操作状态下将参考装置（120）连接到使用装置（110）的开关装置 并且向存储装置（130）提供参考数量（Qref），并且在第二操作条件下，使用参考装置（120）与使用装置（110）断开连接，并将存储装置（130）连接到 使用装置（110），以便将存储的参考数据应用于其中;以及滤波装置（135），用于根据控制的切换将开关装置（122）保持在第二操作状态中的过滤周期（Tf） 信号（Sh）。

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