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    Liquid crystal display having additional signal lines to define additional pixel regions
    33.
    发明授权
    Liquid crystal display having additional signal lines to define additional pixel regions 有权
    液晶显示器具有额外的信号线以限定附加的像素区域

    公开(公告)号：US07511793B2

    公开(公告)日：2009-03-31

    申请号：US11743378

    申请日：2007-05-02

    Applicant: Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

    Inventor： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

    IPC: G02F1/1345 ,  G02F1/1343 ,  G02F1/136

    CPC classification number: G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

    Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.

    Abstract translation: 在液晶显示器中，多个栅极线和数据线设置在包括显示区域作为屏幕的第一基板上，以及在显示区域外部的外围区域，其中多个像素电极电连接到栅极线 和数据线，并且一些像素电极延伸到位于周边区域中; 并且可选地，在与第一基板相对设置的第二基板上形成黑矩阵，用于屏蔽位于周边区域中的像素电极的延伸部分，在第一和第二基板上形成定向膜的摩擦方向朝向 位于外围区域的像素电极的延伸部分，使得取向膜表面上的杂质离子沿着摩擦方向行进，以在像素电极的延伸部分处停止，并且屏蔽由杂质离子引起的图像缺陷区域 与黑色矩阵。

    Electron emission device, electron emission display device including the electron emission device, and method of driving the electron emission device
    36.
    发明申请
    Electron emission device, electron emission display device including the electron emission device, and method of driving the electron emission device 失效
    电子发射装置，包括电子发射装置的电子发射显示装置和驱动电子发射装置的方法

    公开(公告)号：US20070120776A1

    公开(公告)日：2007-05-31

    申请号：US11510560

    申请日：2006-08-28

    Applicant: Sung-Hee Cho ,  Jong-Hwan Park

    Inventor： Sung-Hee Cho ,  Jong-Hwan Park

    IPC: G09G3/22

    CPC classification number: G09G3/22 ,  G09G3/2014 ,  G09G2310/06 ,  G09G2330/021

    Abstract: An electron emission device that is driven at a low voltage has lower power consumption, and can be mass-produced. An electron emission display device includes the electron emission device, The electron emission device includes: a base substrate; a cathode electrode disposed on the base substrate; an electron emission source disposed on the cathode electrode; a data electrode disposed above the electron emission source; a scan electrode disposed above the data electrode; and insulating layers insulating each electrode from the other electrodes. A method of driving the electron emission device includes maintaining a voltage at the cathode electrode of below 0 V or a ground level, maintaining a positive voltage at the scan electrode, and maintaining a voltage at the data electrode of below 0 V; and intermittently providing a positive voltage at the data electrode for a predetermined period of time such that electrons can travel toward the scan electrode for the predetermined period of time.

    Abstract translation: 以低电压驱动的电子发射装置具有较低的功耗，并且可以批量生产。 电子发射显示装置包括电子发射装置。电子发射装置包括：基底; 设置在所述基底基板上的阴极电极; 设置在阴极上的电子发射源; 设置在电子发射源上方的数据电极; 设置在所述数据电极上方的扫描电极; 绝缘层将每个电极与其它电极绝缘。 驱动电子发射器件的方法包括：将阴极电压维持在0V以下或接地电平，维持扫描电极处的正电压，并保持数据电极处的电压低于0V; 并且在数据电极上间歇地提供正电压达预定时间段，使得电子可以朝着扫描电极行进预定的时间段。

    ELECTRON EMISSION SOURCE, METHOD OF PREPARING THE SAME, AND ELECTRON EMISSION DEVICE USING THE ELECTRON EMISSION SOURCE
    37.
    发明申请
    ELECTRON EMISSION SOURCE, METHOD OF PREPARING THE SAME, AND ELECTRON EMISSION DEVICE USING THE ELECTRON EMISSION SOURCE 审中-公开
    电子发射源，其制备方法和使用电子发射源的电子发射装置

    公开(公告)号：US20060255297A1

    公开(公告)日：2006-11-16

    申请号：US11380676

    申请日：2006-04-28

    Applicant: Jong-Woon Moon ,  Sung-Hee Cho ,  Jae-Sang Ha

    Inventor： Jong-Woon Moon ,  Sung-Hee Cho ,  Jae-Sang Ha

    IPC: G21G4/00

    CPC classification number: H01J1/304 ,  B82Y10/00 ,  H01J9/025 ,  H01J2201/30469

    Abstract: An electron emission source including a carbon-based material and a UV shielding material, a method of preparing the same, and an electron emission device using the electron emission source are provided. The UV shielding material is added to an electron emission source forming composition to more easily control the sharpness of an electron emission source tip. The electron emission source composition may include a carbon-based material, a vehicle including a resin and a solvent, and a UV shielding material.

    Abstract translation: 提供了包括碳基材料和UV屏蔽材料的电子发射源，其制备方法和使用电子发射源的电子发射装置。 将紫外线屏蔽材料添加到电子发射源形成组合物中以更容易地控制电子发射源尖端的清晰度。 电子发射源组合物可以包括碳基材料，包括树脂和溶剂的载体和UV屏蔽材料。

    Power glitch free internal voltage generation circuit
    38.
    发明授权
    Power glitch free internal voltage generation circuit 失效
    电源无毛刺内部电压产生电路

    公开(公告)号：US06936998B2

    公开(公告)日：2005-08-30

    申请号：US10620547

    申请日：2003-07-16

    Applicant: Sung-Hee Cho

    Inventor： Sung-Hee Cho

    IPC: G11C5/14 ,  G05F1/56 ,  G05F3/24 ,  G05F1/40 ,  G05F1/10

    CPC classification number: G05F3/242 ,  G05F1/56

    Abstract: A power glitch free internal voltage generation circuit includes: a voltage divider for dividing level of an internal voltage; a reference voltage generator generating a reference voltage having a predetermined voltage level by dividing a level of an external voltage; a comparator connected to the external voltage and the internal voltage and comparing the divided internal voltage with the reference voltage to generate a compared output; and a driver for supplying the external voltage to the internal voltage in response to the output of the comparator. In this manner, a high voltage level from either of the external voltage and the internal voltage is used as a source of the comparator. This, in turn, stably maintains the internal voltage because the driver for transferring the external voltage to the internal voltage is intercepted in the case where a glitch occurs that lowers the external voltage to a level lower than the internal voltage.

    Abstract translation: 电源无故障内部电压产生电路包括：分压器，用于分压内部电压的电平; 参考电压发生器，通过分压外部电压的电平来产生具有预定电压电平的参考电压; 比较器连接到外部电压和内部电压，并将分压的内部电压与参考电压进行比较以产生比较的输出; 以及用于响应于比较器的输出将外部电压提供给内部电压的驱动器。 以这种方式，使用来自外部电压和内部电压的任何一个的高电压电平作为比较器的源。 这反过来稳定地维持内部电压，因为在发生将外部电压降低到低于内部电压的电平的毛刺的情况下，外部电压转移到内部电压的驱动器被截断。

    Nonvolatile semiconductor memories with a NAND logic cell structure
    39.
    发明授权
    Nonvolatile semiconductor memories with a NAND logic cell structure 失效
    具有NAND逻辑单元结构的非易失性半导体存储器

    公开(公告)号：US06650567B1

    公开(公告)日：2003-11-18

    申请号：US08213004

    申请日：1994-03-14

    Applicant: Sung-Hee Cho ,  Sang-Ki Hwang ,  Hyong-Gon Lee

    Inventor： Sung-Hee Cho ,  Sang-Ki Hwang ,  Hyong-Gon Lee

    IPC: G11C1604

    CPC classification number: G11C16/0483 ,  G11C17/123

    Abstract: A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

    Abstract translation: 具有由NAND结构的第一至第N（N = 2,3,4 ...）个存储单元晶体管组成的多个存储串组成的单元阵列的非易失性半导体集成电路包括多个第一串选择 与第一存储单元晶体管串联连接的晶体管，以及与第N个存储单元晶体管串联连接的多个第二串选择晶体管。 串联连接到第一和第N存储单元晶体管的串选择晶体管之一具有连接到接地连接点的控制端子，从而具有接地选择功能以及串选择功能。

    Circuit for repairing defective read only memories with redundant NAND string
    40.
    发明授权
    Circuit for repairing defective read only memories with redundant NAND string 失效
    用冗余NAND串修复有缺陷的只读存储器的电路

    公开(公告)号：US5434814A

    公开(公告)日：1995-07-18

    申请号：US132175

    申请日：1993-10-06

    Applicant: Sung-Hee Cho ,  Kang-Deog Suh ,  Hyong-Gon Lee ,  Jae-Yeong Do

    Inventor： Sung-Hee Cho ,  Kang-Deog Suh ,  Hyong-Gon Lee ,  Jae-Yeong Do

    IPC: G11C17/00 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04 ,  H01L27/00 ,  G11C11/40

    CPC classification number: G11C29/822

    Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

    Abstract translation: 具有缺陷修复功能的掩模ROM存储对应于缺陷存储单元的地址信号，然后根据存储的地址信号是否与外部提供的地址信号相同，选择性地激活冗余行解码器或行解码器。 掩模ROM包括通过在字线方向上分组以行和列排列的多个只读存储器单元形成的第一和第二存储单元阵列; 第一和第二行解码器，用于组合外部提供的行地址信号，以选择性地驱动第一和第二存储单元阵列的字线; 以及行解码器选择器，用于根据包括第一存储单元阵列的缺陷存储单元的行块存储其中的地址信号，以便在外部行地址信号等于第一行解码器时使第一行解码器失活，并激活第二行解码器 存储在行解码器选择器中的地址信号。

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