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    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    31.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
    半导体结构及其工艺

    公开(公告)号：US20160336269A1

    公开(公告)日：2016-11-17

    申请号：US14709500

    申请日：2015-05-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

    Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

    SEMICONDUCTOR DEVICE
    35.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140361386A1

    公开(公告)日：2014-12-11

    申请号：US14465579

    申请日：2014-08-21

    Applicant: United Microelectronics Corp.

    Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

    IPC: H01L29/78 ,  H01L29/49

    CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.

    Abstract translation: 提供了一种包括基板，栅极结构，第二介电层和源极/漏极区域的半导体器件。 第一电介质层设置在基板上，并且第一介电层在其中具有沟槽。 栅极结构设置在沟槽中的衬底上，并且包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括TiAl 3相金属层。 布置在沟槽的侧壁上的功函数金属层的高度低于第一电介质层的顶表面的高度。 金属层填充沟槽。 第二电介质层设置在栅极结构和衬底之间。 源极/漏极区域在栅极结构的两侧设置在衬底中。

    METHOD OF FORMING METAL GATE
    37.
    发明申请
    METHOD OF FORMING METAL GATE 审中-公开
    形成金属门的方法

    公开(公告)号：US20140120711A1

    公开(公告)日：2014-05-01

    申请号：US13661998

    申请日：2012-10-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun

    IPC: H01L21/283

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

    Abstract: Provided is a method of forming a metal gate including the following steps. A dielectric layer is formed on a substrate, wherein a gate trench is formed in the dielectric layer and a gate dielectric layer is formed in the gate trench. A first metal layer is formed in the gate trench by applying a AC bias between a target and the substrate during physical vapor deposition. A second metal layer is formed in the gate trench by applying a DC bias between the target and the substrate during physical vapor deposition.

    Abstract translation: 提供一种形成金属栅极的方法，包括以下步骤。 在衬底上形成介电层，其中在电介质层中形成栅极沟槽，并且在栅极沟槽中形成栅极电介质层。 通过在物理气相沉积期间在靶和衬底之间施加AC偏压，在栅极沟槽中形成第一金属层。 通过在物理气相沉积期间在靶和衬底之间施加DC偏压，在栅极沟槽中形成第二金属层。

    Semiconductor Device Having a Metal Gate and Fabricating Method Thereof
    38.
    发明申请
    Semiconductor Device Having a Metal Gate and Fabricating Method Thereof 有权
    具有金属栅极的半导体器件及其制造方法

    公开(公告)号：US20140097507A1

    公开(公告)日：2014-04-10

    申请号：US14105198

    申请日：2013-12-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Chin-Fu Lin ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chien-Hao Chen

    IPC: H01L29/49 ,  H01L21/28

    CPC classification number: H01L21/28026 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

    Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 提供基板，并且在其上形成栅极电介质和功函数金属层，其中功函数金属层在栅极电介质层上。 然后，在功函数金属层上形成顶部阻挡层。 形成顶部阻挡层的步骤包括增加顶部阻挡层中边界保护材料的浓度。 最后，在顶部阻挡层上形成金属层。 本发明还提供一种具有金属栅极的半导体器件。

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