公开(公告)号：EP3275009A1

公开(公告)日：2018-01-31

申请号：EP16769611.1

申请日：2016-03-23

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： RINCK, Helmut ,  BAUER, Gernot ,  ZRILE, Robert ,  SCHACHTSCHNEIDER, Kai-Alexander ,  OTTE, Michael ,  WIESNER, Harald

IPC: H01L21/28

CPC classification number: H01L24/13 ,  H01L23/5226 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05558 ,  H01L2224/05657 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01078 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01051

Abstract: A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

公开(公告)号：JP2004363583A

公开(公告)日：2004-12-24

申请号：JP2004150986

申请日：2004-05-20

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社

Inventor： SEO JUNG-HUN ,  CHOI GIL-HEYUN ,  LEE JONG-MYEONG ,  PARK HEE-SOOK

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a conductive structure of a semiconductor. SOLUTION: The method includes a process of forming a lower conductive pattern on a semiconductor substrate and after the vapor deposition of a barrier metal film using a metal organic precursor, cleaning the vapor-deposited barrier metal film. It is desirable that the process of cleaning the barrier metal film is carried out using a process gas including a TiCl 4 gas and argon gas at a temperatures between 200°C and 500°C. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：EP2863430B1

公开(公告)日：2017-04-12

申请号：EP15150440.4

申请日：2003-07-24

Applicant: Socionext Inc.

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

公开(公告)号：EP2863431A3

公开(公告)日：2015-07-22

申请号：EP15150443.8

申请日：2003-07-24

Applicant: Socionext Inc.

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device comprising: a rectangular semiconductor substrate including a semiconductor circuit region and four corners; a first insulating film formed above the rectangular semiconductor substrate; a second insulating film formed above the first insulating film; a plurality of guard rings which surround the semiconductor circuit region; and a first conductive layer formed in the first insulating film. Each of the guard rings comprises a groove-shaped via formed in the second insulating film and connected to the first conductive layer. The groove-shaped via includes a pattern bent twice each time at an angle of larger than 90 degree at each of the four corners, and the pattern is bent totally at 90 degree at each of the four corners of the semiconductor substrate.

公开(公告)号：EP2863430A3

公开(公告)日：2015-07-22

申请号：EP15150440.4

申请日：2003-07-24

Applicant: Socionext Inc.

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device comprising: a substrate; a first insulating film formed on the substrate; an aluminum layer formed above the first insulating film; a first guard ring which includes a first groove-shaped via-hole formed in the first insulating film and a first conductor formed in the first groove-shaped via-hole, the first conductor being connected to the substrate; and a second guard ring which includes a second groove-shaped via-hole formed in the first insulating film and a second conductor formed in the second groove-shaped via-hole, the second conductor being connected to the substrate. The second guard ring is surrounded by the first guard ring in a plan view, and the first guard ring is connected to the aluminum layer. Each of the first groove-shaped via-hole and the second groove-shaped via-hole includes a pattern bent twice each time at an inner angle of larger than 90 degree at each of four corners of the semiconductor device in a plan view.

公开(公告)号：EP2175486A3

公开(公告)日：2012-03-28

申请号：EP10000803.6

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective fil ling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 该半导体器件包括：在衬底10上形成的绝缘膜40,42; 埋入绝缘膜40,42的至少一个表面侧的配线58; 绝缘膜60,62，形成在绝缘膜42上，并包括具有弯曲成直角图案的孔状通孔60和槽状通孔66a; 以及掩埋在孔状通孔60和槽状通孔66a中的掩埋导体70,72a，其中槽状通孔66a形成为具有小于孔的宽度的宽度 从而防止了埋入导体的缺陷填充，并且可以防止层间绝缘膜的破裂。 可以减少导体插头上的台阶，使得台阶不会影响上互连层和绝缘层。 因此，可以防止与上互连层的接触不良以及形成膜时发生的问题，并且因此半导体器件可以具有高水阻和高互连可靠性。

公开(公告)号：EP2863431B1

公开(公告)日：2017-04-26

申请号：EP15150443.8

申请日：2003-07-24

Applicant: Socionext Inc.

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 该半导体器件包括：在衬底10上形成的绝缘膜40,42; 埋入绝缘膜40,42的至少一个表面侧的配线58; 绝缘膜60,62，形成在绝缘膜42上，并包括具有弯曲成直角图案的孔状通孔60和槽状通孔66a; 以及掩埋在孔状通孔60和槽状通孔66a中的掩埋导体70,72a，其中槽状通孔66a形成为具有小于孔的宽度的宽度 从而防止埋入导体的填充不良，并且可以防止层间绝缘膜的破裂。 可以减少导体插头上的台阶，使得台阶不会影响上互连层和绝缘层。 因此，可以防止与上互连层的接触不良以及形成膜时发生的问题，并且因此半导体器件可以具有高水阻和高互连可靠性。

公开(公告)号：EP2175487B1

公开(公告)日：2015-03-11

申请号：EP10000804.4

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：EP2175487A3

公开(公告)日：2012-04-18

申请号：EP10000804.4

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：EP2175486A2

公开(公告)日：2010-04-14

申请号：EP10000803.6

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective fil ling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此，能够防止埋入导体的缺陷，能够防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。