公开(公告)号：US20150179603A1

公开(公告)日：2015-06-25

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/306

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

Abstract translation: 一种制造复合结构的方法，包括至少一个第一晶片与第二晶片的直接结合，并且包括启动键合波的传播的步骤，其中在所述第一和第二晶片传播之后的所述第一和第二晶片之间的结合界面 波具有小于或等于0.7J / m 2的结合能。 启动粘合波传播的步骤是在以下一个或多个条件下进行的：将晶片放置在小于20毫巴的压力的环境中和/或施加到两个晶片之一的机械压力 在0.1MPa和33.3MPa之间。 该方法还包括在开始粘合波的传播的步骤之后，确定在两个晶片的接合期间引起的应力水平的步骤，根据使用第二晶片计算出的应力参数Ct来确定应力水平 公式Ct = Rc / Ep，其中：Rc对应于两晶片组件的曲率半径（km），Ep对应于两晶片组件的厚度（μm）。 该方法还包括当确定的应力Ct大于或等于0.07时验证接合的步骤。

公开(公告)号：US20130026490A1

公开(公告)日：2013-01-31

申请号：US13194585

申请日：2011-07-29

Applicant: Victor H. Cruz ,  David Francis Courtney

Inventor： Victor H. Cruz ,  David Francis Courtney

IPC: H01L21/56 ,  H01L29/20 ,  H01L29/12 ,  H01L23/495

CPC classification number: H01L23/291 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/37184 ,  H01L2224/37639 ,  H01L2224/37655 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/097 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/201 ,  H01L2924/20111 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01005

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract translation: 用于非轴向电子器件的高温非空腔封装是使用玻璃陶瓷化合物设计的，其能够在高于300-400℃的温度下连续组装和操作。金属钎焊，例如银，银胶体或 铜，用于连接半导体管芯，引线框架和连接器。 这些部件也是热匹配的，使得封装可以在高温下连续地组装和操作，并且可承受极端的温度变化，而不会发生键失效或者由于热失配引起的封装破裂。

公开(公告)号：US20100187563A1

公开(公告)日：2010-07-29

申请号：US12691947

申请日：2010-01-22

Applicant: Masafumi Kuramoto ,  Satoru Ogawa ,  Miki Niwa

Inventor： Masafumi Kuramoto ,  Satoru Ogawa ,  Miki Niwa

IPC: H01L33/00 ,  H01L21/60

CPC classification number: H01L33/44 ,  H01L23/08 ,  H01L23/293 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2712 ,  H01L2224/2745 ,  H01L2224/275 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83487 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0541 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/201 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/3025 ,  H01L2933/0066 ,  H01S5/0226 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2224/05599

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, temporarily bonding the semiconductor element and the base by applying a pressure or an ultrasonic vibration to the semiconductor element or the base, and permanently bonding the semiconductor element and the base by applying heat having a temperature of 150 to 900° C. to the semiconductor device and the base.

Abstract translation: 本发明的目的是提供一种用于制造具有低电阻的导电构件的方法，并且使用不含粘合剂的低成本稳定的导电材料组合物获得导电构件。 一种制造半导体器件的方法，其中设置在基底表面上的银或氧化银和设置在半导体元件的表面上的银或银氧化物结合，包括以下步骤：将半导体元件布置在基底上，使得银 或设置在半导体元件的表面上的氧化银与设置在基板的表面上的银或氧化银接触，通过向半导体元件或基底施加压力或超声波振动来临时接合半导体元件和基座 并且通过向半导体器件和基底施加温度为150至900℃的热而将半导体元件和基底永久地接合。

公开(公告)号：WO2015152197A1

公开(公告)日：2015-10-08

申请号：PCT/JP2015/060041

申请日：2015-03-31

Applicant: 日鉄住金マイクロメタル株式会社 ,  新日鉄住金マテリアルズ株式会社

Inventor： 山田　隆 ,  小田　大造 ,  大石　良 ,  榛原　照男 ,  宇野　智裕

IPC: H01L21/60 ,  B21C1/00 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14

CPC classification number: H01L24/45 ,  B21C1/00 ,  B21C1/003 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45012 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2924/00011 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/01201 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/12044 ,  H01L2924/00015 ,  H01L2224/45664 ,  H01L2924/01049 ,  H01L2924/01045 ,  H01L2924/01004 ,  H01L2924/01005

Abstract: 　リーニング不良とスプリング不良をともに抑制するため、（１）ワイヤ中心を含みワイヤ長手方向に平行な断面（ワイヤ中心断面）において長径ａと短径ｂの比ａ／ｂが１０以上でありさらに面積が１５μｍ 2 以上である結晶粒（繊維状組織）が存在せず、（２）ワイヤ中心断面における、ワイヤ長手方向の結晶方位を測定した結果、前記ワイヤ長手方向に対して角度差が１５°以下である結晶方位＜１００＞の存在比率が面積率で１０％以上５０％未満であり、（３）ワイヤ表面における、ワイヤ長手方向の結晶方位を測定した結果、前記ワイヤ長手方向に対して角度差が１５°以下である結晶方位＜１００＞の存在比率が面積率で７０％以上であることを特徴とする半導体装置用ボンディングワイヤ。伸線工程中に減面率が１５．５％以上の伸線加工を少なくとも１回行い、最終熱処理温度と最終前熱処理温度を所定範囲とする。

Abstract translation: 与半导体器件一起使用的接合线，为了使倾斜问题和弹簧问题最小化，其特征在于：（1）与导线的长度方向平行且包含线的中心的横截面 线中心横截面）不含长轴（a）/短轴（b）比（a / b）为10以上且面积为15μm2以上的晶粒（纤维结构体） （2）电线中心横截面面积的至少10％但小于50％在电线长度方向的15°内呈现<100°的晶体取向; 和（3）电线表面的至少70％的面积在电线的长度方向的15°内呈现<100°的晶体取向。 在拉丝工序中，进行至少15.5％的面积减少的拉丝至少进行一次，最后的热处理温度和最终的预热处理温度设定在规定范围内。

公开(公告)号：WO2015057605A1

公开(公告)日：2015-04-23

申请号：PCT/US2014/060340

申请日：2014-10-14

Applicant: CORNING INCORPORATED

Inventor： ENICKS, Darwin Gene ,  KEECH, John Tyler ,  SHOREY, Aric Bruce ,  THOMAS, Windsor Pipes, III

IPC: H01L21/683 ,  H01L21/48

CPC classification number: H01L21/6835 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/83052 ,  H01L2224/8385 ,  H01L2924/01029 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/12 ,  H01L2924/12041 ,  H01L2924/1432 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/201 ,  H01L2924/20107 ,  H01L2924/2011 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00

Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Abstract translation: 一种经由表面改性层（30）设置在载体（10）上以形成制品（2）的薄片（20），其中所述制品可以经受高温处理，如在FEOL半导体加工中，不排气并具有 在加工过程中，薄片保持在载体上而不与其分离，然后在室温剥离力下分离，使得薄片和载体中较薄的一个完整。 具有通孔（60）阵列（50）的插入件（56）可以形成在薄片上，以及形成在插入件上的器件（66）。 或者，薄片可以是在FEOL处理期间形成半导体电路的基板。

公开(公告)号：US20180218988A1

公开(公告)日：2018-08-02

申请号：US15882680

申请日：2018-01-29

Applicant: KULITE SEMICONDUCTOR PRODUCTS, INC.

Inventor： Sorin Stefanescu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/45144 ,  H01L2224/45169 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/351 ,  H01L2924/365

Abstract: Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.

公开(公告)号：US09601400B2

公开(公告)日：2017-03-21

申请号：US14827142

申请日：2015-08-14

Applicant: Semtech Corporation

Inventor： Victor Hugo Cruz ,  David Francis Courtney

IPC: H01L29/12 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/291 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/37184 ,  H01L2224/37639 ,  H01L2224/37655 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/097 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/201 ,  H01L2924/20111 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01005

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

公开(公告)号：US09355881B2

公开(公告)日：2016-05-31

申请号：US14182689

申请日：2014-02-18

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Eva-Maria Hess ,  Edward Fuergut ,  Christian Schweiger

IPC: H01L21/683 ,  H01L21/268 ,  H01L21/304 ,  H01L21/762 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/6835 ,  H01L21/268 ,  H01L21/304 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76251 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00 ,  H01L2224/82 ,  H05K3/467 ,  H01L2224/03 ,  H01L2924/01029

Abstract: A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的载流子和半导体晶片。 该方法包括将介电材料施加到载体或半导体晶片，并通过电介质材料将半导体晶片接合到载体上。 该方法包括处理半导体晶片并从半导体晶片去除载体，使得介电材料保留在半导体晶片上，以提供包括电介质材料的半导体器件。

公开(公告)号：US20160141266A1

公开(公告)日：2016-05-19

申请号：US14800613

申请日：2015-07-15

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Kyoung-Kook HONG ,  Hyun Woo NOH ,  Youngkyun JUNG ,  Dae Hwan CHUN ,  Jong Seok LEE ,  Su Bin KANG

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/02 ,  B23K35/26 ,  B23K1/00 ,  H05K3/34

CPC classification number: H01L24/83 ,  B23K20/026 ,  B23K20/16 ,  B23K20/233 ,  B23K35/025 ,  B23K35/264 ,  B23K35/3006 ,  B23K2101/42 ,  B23K2103/166 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13294 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/29294 ,  H01L2224/29313 ,  H01L2224/29339 ,  H01L2224/32227 ,  H01L2224/32505 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81825 ,  H01L2224/8184 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2924/00015 ,  H01L2924/10272 ,  H01L2924/201 ,  H01L2924/2075 ,  H01L2924/20751 ,  H05K3/341 ,  H05K3/3463 ,  H05K2201/10166 ,  H05K2203/1131 ,  H01L2224/29388 ,  H01L2924/00014 ,  H01L2224/13388 ,  H01L2924/00012

Abstract: A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of silver particles and a plurality of bismuth particles. The method further includes disposing the semiconductor on the substrate and forming a bonding layer by heating the silver paste, wherein the semiconductor and the substrate are bonded to each other by the bonding layer.

Abstract translation: 用银膏粘合的方法包括用银膏涂覆半导体器件或衬底。 银糊含有多个银颗粒和多个铋颗粒。 该方法还包括将半导体布置在衬底上并通过加热银膏形成接合层，其中半导体和衬底通过接合层彼此接合。

公开(公告)号：US20160104687A1

公开(公告)日：2016-04-14

申请号：US14893789

申请日：2015-03-31

Applicant: NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL & SUMIKIN MATERIALS CO. LTD.

Inventor： Takashi YAMADA ,  Daizo ODA ,  Ryo OISHI ,  Teruo HAIBARA ,  Tomohiro UNO

IPC: H01L23/00 ,  C22C5/06 ,  C22C5/08 ,  B21C1/00 ,  C22F1/14

CPC classification number: H01L24/45 ,  B21C1/00 ,  B21C1/003 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45012 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2924/00011 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/01201 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/12044 ,  H01L2924/00015 ,  H01L2224/45664 ,  H01L2924/01049 ,  H01L2924/01045 ,  H01L2924/01004 ,  H01L2924/01005

Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 10% to less than 50%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 70% or more. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 线中心横截面的方向，晶体方向<100>相对于导线纵向方向的角度差为15°以下的面积比为10％以上且小于50％，（3 ）当在线表面测量线长度方向的晶体方向时，晶体方向<100>与线长度方向的角度差为15°以下的面积比为70％以上 。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。