公开(公告)号：KR1020020096006A

公开(公告)日：2002-12-28

申请号：KR1020010034680

申请日：2001-06-19

Applicant: 엘지전자 주식회사

Inventor： 박준한

IPC: H03M1/12

CPC classification number: H03M1/06 ,  H03M2201/196 ,  H03M2201/622

Abstract: PURPOSE: An apparatus and a method for improving a resolution of an input signal in a mobile station modem(MSM) are provided to receive an input signal with a desired resolution since an input signal inputted from an external interface device to the MSM is digital signal processed at a processor without depending on an analog digital(AD) converter in the MSM when the input signal from the external interface device to the MSM is quantized. CONSTITUTION: An apparatus for improving a resolution of an input signal in a mobile station modem(MSM)(130) includes a subtraction block(110) for receiving an input signal from an external interface device and for subtracting the input signal and a feedback signal, an AD converter(131) of the MSM(130) for receiving the output signal of the subtraction block(110) through an integrator(120), a processor(132) for implementing a calculation by receiving the output signal of the AD converter(131) and a feedback terminal(140) for feeding back the control signal of the processor(132) to the subtraction block(110).

Abstract translation: 目的：提供一种用于提高移动台调制解调器（MSM）中的输入信号的分辨率的装置和方法，用于以期望的分辨率接收输入信号，因为从外部接口装置输入到MSM的输入信号是数字信号 在来自外部接口设备到MSM的输入信号被量化时，在处理器处理而不依赖于MSM中的模拟数字（AD）转换器。 一种用于提高移动台调制解调器（MSM）（130）中的输入信号的分辨率的装置，包括：减法块（110），用于从外部接口装置接收输入信号，并减去输入信号和反馈信号 ，用于通过积分器（120）接收减法块（110）的输出信号的MSM（130）的AD转换器（131），用于通过接收AD转换器的输出信号来实现计算的处理器（132） （131）和用于将处理器（132）的控制信号反馈到减法模块（110）的反馈终端（140）。

公开(公告)号：KR1020000065904A

公开(公告)日：2000-11-15

申请号：KR1019990012657

申请日：1999-04-10

Applicant: 삼성전자주식회사

Inventor： 구형완

IPC: H03M1/66

CPC classification number: H03M1/765 ,  H03M2201/622

Abstract: PURPOSE: A digital-analog converter is provided to output signals with high accuracy by supplying uniform amount of current to a current-voltage converter by changing an output impedence of a switching part in response to the change of voltage level of an output signal from the current-voltage converter. CONSTITUTION: A digital-analog converter includes a current supply(100), a latch(200), a switch(300), a decoder(400) and current-voltage converter(500). The current supply supplies currents each of which has a predetermined amount to the switch. The latch latches external data having plural bits. The switch switches the currents from the current supply under the control of the data from the latch. The decoder decodes corresponding data among the data pieces output from the latch to generate a switching control signals. The current-voltage converter converts current corresponding to sum of the currents transmitted through the switch into a voltage to output it as an output signal under the control of the switching control signal. The current-voltage converter also varies the output impedance of the switch under the control of the switching control signal. When the voltage level of the output signal from the current-voltage converter is varied, the output impedance of the switch is changed to allow the currents from the current supply to be provided to the current-voltage converter, to thereby output an output signal with improved accuracy.

Abstract translation: 目的：提供数字模拟转换器，通过根据来自电流 - 电压转换器的输出信号的电压电平的变化改变开关部分的输出阻抗，向电流 - 电压转换器提供均匀的电流，以高精度输出信号 电流 - 电压转换器。 构成：数模转换器包括电流源（100），锁存器（200），开关（300），解码器（400）和电流 - 电压转换器（500）。 电流源向开关提供各自具有预定量的电流。 锁存器锁存具有多个位的外部数据。 开关在来自锁存器的数据控制下切换来自电流源的电流。 解码器解码从锁存器输出的数据段中的对应数据，以产生切换控制信号。 电流 - 电压转换器将对应于通过开关传输的电流之和的电流转换成电压，以在开关控制信号的控制下将其输出为输出信号。 电流 - 电压转换器还可以在开关控制信号的控制下改变开关的输出阻抗。 当来自电流 - 电压转换器的输出信号的电压电平发生变化时，开关的输出阻抗发生变化，使来自电流源的电流被提供给电流 - 电压转换器，从而输出输出信号 提高准确度。

公开(公告)号：KR1020000044788A

公开(公告)日：2000-07-15

申请号：KR1019980061288

申请日：1998-12-30

Applicant: 동부대우전자 주식회사

Inventor： 김종락

IPC: H03M7/30

CPC classification number: H03M1/48 ,  H03M2201/622

Abstract: PURPOSE: A quantization decoding apparatus is provided to reduce a quantization error by performing a quantization decoding on the basis of a statistical characteristic of a data sequency extracted from bit values from a quantization encoder. CONSTITUTION: A quantization decoding apparatus comprises a bit discriminating part(305), a possibility value calculating part(310), first and second switching parts(315,320) and first and second quantization representation value generating parts(325,350). The bit discriminating part(305) judges whether a present input bit is '0' or '1', and generates a discrimination signal according to the result. The possibility value calculating part(310) calculates a possibility with reference to the discrimination signal. The first switching part(315) provides the input bit to either one of the first and second quantization representation value generating parts(325,350) on the basis of the discrimination signal so that the bit of '0' is inputted to the first quantization representation value generating part(325) and the bit of '1' is inputted to the second quantization representation value generating parts(350). The second switching part(320) provides the possibility value to either one of the first and second quantization representation value generating parts(325,350) on the basis of the discrimination signal. The first quantization representation value generating parts(325) generates a first representation value in response to the possibility value, when the bit of '1' is inputted. The second quantization representation value generating parts(330) generates a second representation value in response to the possibility value, when the bit of '0' is inputted.

Abstract translation: 目的：提供一种量化解码装置，用于通过根据从量化编码器的比特值提取的数据序列的统计特性进行量化解码来减少量化误差。 构成：量化解码装置包括比特识别部分（305），可能值计算部分（310），第一和第二切换部分（315,320）以及第一和第二量化表示值生成部分（325,350）。 比特识别部（305）判断当前输入比特是“0”还是“1”，根据该结果生成判别信号。 可能性值计算部（310）参照鉴别信号计算可能性。 第一切换部分（315）基于鉴别信号将输入比特提供给第一和第二量化表示值生成部分（325,350）中的任何一个，使得比特“0”被输入到第一量化表示值 产生部分（325）并且位“1”被输入到第二量化表示值生成部分（350）。 第二切换部（320）基于判别信号，提供第一和第二量化表示值生成部（325,350）中的任一个的可能性值。 当输入“1”的比特时，第一量化表示值产生部分（325）响应于可能性值产生第一表示值。 当输入“0”的比特时，第二量化表示值产生部分（330）响应于可能性值产生第二表示值。

公开(公告)号：KR1020000044724A

公开(公告)日：2000-07-15

申请号：KR1019980061224

申请日：1998-12-30

Applicant: 동부대우전자 주식회사

Inventor： 김종락

IPC: H03M7/30

CPC classification number: H03M1/48 ,  H03M2201/622

Abstract: PURPOSE: A quantization decoding apparatus is provided to reduce a quantization error by performing a quantization decoding on the basis of deducted statistical characteristic of each sequence. CONSTITUTION: A quantization decoding apparatus comprises a quantization judging part(305) which judges whether an input bit is '1' or '0' and provides a judgement signal to a possibility value calculating part(310). The possibility value calculating part(310) calculates a possibility on the basis of the judgement signal. A first quantization representation value generating part(325) judges whether a quantized bit stream of a first stage is '0' or '1', and determines a quantization representation value corresponding to an input bit as an intermediate value of a quantization period. A counter(315) counts the number of bits of a bit stream quantized by a quantizer of an L-th stage. In case of decoding a bit stream from a quantization encoder of the first stage, a control part(315) controls so as for a second quantization representation value generating part(330) to be operated when a count value of the counter(315) is more than a predetermined value(R). The second quantization representation value generating part(330) judges whether a quantized bit stream of the L-th stage is '1' or '0'. The second quantization representation value generating part(330) generates a representation value according to the possibility from the possibility value calculating part(310) when the input bit is '0'.

Abstract translation: 目的：提供量化解码装置，通过基于每个序列的扣除统计特性进行量化解码来减少量化误差。 构成：量化解码装置包括判定输入比特为“1”还是“0”的量化判定部（305），并将判定信号提供给可能值计算部（310）。 可能值计算部（310）根据判断信号计算出可能性。 第一量化表示值生成部（325）判断第一级的量化比特流是否为“0”或“1”，并且将与输入比特对应的量化表示值确定为量化周期的中间值。 计数器（315）对由第L级的量化器量化的比特流的比特数进行计数。 在对来自第一级的量化编码器的比特流进行解码的情况下，控制部（315）进行控制，以使当第二量化表示值生成部（330）的计数值为 大于预定值（R）。 第二量化表示值生成部（330）判断第L级的量化比特流是“1”还是“0”。 当输入比特为“0”时，第二量化表示值产生部分（330）根据可能性值计算部分（310）的可能性产生表示值。