公开(公告)号：CN105991137A

公开(公告)日：2016-10-05

申请号：CN201610164945.6

申请日：2016-03-21

Applicant: 德克萨斯仪器股份有限公司

Inventor： J·谭古都 ,  S·巴拉德瓦杰 ,  S·兰加查理

IPC: H03M1/12

CPC classification number: H03H11/04 ,  H03H17/0275 ,  H03H17/028 ,  H03H17/0642 ,  H03M1/126 ,  H03M2201/196

Abstract: 本发明涉及可变分数速率数字重采样的系统和方法。本文所公开的可变分数速率数字重采样的系统和方法的示例性实施例实现可变速率转换。在示例性实施例中，输入样本在升采样器(510)中以因子N被升采样，升采样器(510)后是滤波器(520)，之后输入样本通过线性插值器(540)。滤波器(520)清除由于升采样操作产生的信号频谱图像。

公开(公告)号：CN105634494A

公开(公告)日：2016-06-01

申请号：CN201510971691.4

申请日：2015-12-22

Applicant: 中国电子科技集团公司第五十研究所

Inventor： 杨成

IPC: H03M1/54

CPC classification number: H03M1/54 ,  H03M2201/196 ,  H03M2201/625

Abstract: 本发明提供了一种射频信号模数转换的方法，包括步骤(1)将被采样信号的电平范围划分为若干个电平区域，设置若干个采样电路的电平范围与所述若干个电平区域匹配；(2)每个采样电路基于预定限幅和预定参考电平确定被采样信号的电平的特定电平区域；(3)所述若干个采样电路基于采样时钟同步对所述若干个电平区域和所述预定参考电平进行采样。本发明的技术方案实现无线通信接收射频信号直接数字化，提高分辨率。

公开(公告)号：US4010422A

公开(公告)日：1977-03-01

申请号：US409425

申请日：1973-10-25

Applicant: Kornelis Jan Wouda

Inventor： Kornelis Jan Wouda

IPC: H03M1/00 ,  H04B14/04 ,  H04B1/04

CPC classification number: H04B14/04 ,  H03M1/00 ,  H04B14/048 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2344 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/425 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8124

Abstract: A non-linear pulse code modulator wherein input signals are coded into digital representations of amplitude range segments and amplitude in excess of the minimum amplitude within the respective range segment uses a first analog-to-digital converter having a sawtooth-shaped control characteristic to determine the amplitude range segment from an input signal sample. The output of the first analog-to-digital converter is used to effectively divide the signal sample by a factor 2.sup.n, where n corresponds to the determined range. The result of the division is then converted in a second analog-to-digital conversion to a digital signal that is combined with the digital range segment signal for transmission thereof.

公开(公告)号：US4862170A

公开(公告)日：1989-08-29

申请号：US171812

申请日：1988-03-22

Applicant: Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

Inventor： Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

IPC: G11B20/10 ,  H03M1/00 ,  H03M1/66

CPC classification number: H03M1/00 ,  H03M2201/03 ,  H03M2201/196 ,  H03M2201/30 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/526 ,  H03M2201/6121 ,  H03M2201/721

Abstract: A digital analog converter which is especially suitable for use in converting a digital audio signal into an analog audio signal includes a unit pulse response signal generator for successively generating unit pulse response signals at a predetermined time interval, a digital data generator for generating digital data at the predetermined time interval, a multiplier for multiplying a unit pulse response signal generated at a certain time by a predetermined item of the digital data, and a mixer for producing an analog signal output by combining the unit pulse response signals that have been multiplied by the digital data.

Abstract translation: 特别适用于将数字音频信号转换为模拟音频信号的数字模拟转换器包括用于以预定的时间间隔连续产生单位脉冲响应信号的单位脉冲响应信号发生器，用于产生数字数据的数字数据发生器 所述预定时间间隔，用于将在某一时间产生的单位脉冲响应信号乘以数字数据的预定项目的乘法器和用于产生模拟信号的混频器，所述混频器通过将已经乘以所述单位脉冲响应信号 数字数据。

公开(公告)号：US4626827A

公开(公告)日：1986-12-02

申请号：US475405

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka ,  Hiroyuki Takekura

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka ,  Hiroyuki Takekura

IPC: H03M1/00 ,  H04B14/04 ,  H03K13/02

CPC classification number: H03M1/00 ,  H04B14/046 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/20 ,  H03M2201/3115 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/531 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/535 ,  H03M2201/648 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8128 ,  H03M2201/834

Abstract: A data compression system comprises an analog-to-digital converter for quantizing the analog signal at a first sampling frequency into a series of digital samples and a memory for storing the digital samples. A control circuit generates a sampling datum indicating a variable sampling frequency lower than the first sampling frequency as a function of the instantaneous frequency of the analog signal for selecting digital samples from the memory, reads the selected digital samples out of the memory means in response to the sampling datum, and forms the sampling datum and the selected digital samples into a data set. A series of data sets may be transmitted to a receiving end of the system or stored in a recording medium. The sampling datum is used to indicate the point at which the digital sample is converted to a corresponding analog value.

Abstract translation: 数据压缩系统包括用于将第一采样频率的模拟信号量化成一系列数字样本的模数转换器和用于存储数字样本的存储器。 控制电路根据用于从存储器中选择数字样本的模拟信号的瞬时频率的函数产生指示低于第一采样频率的可变采样频率的采样数据，以响应于从存储器装置读出所选择的数字样本 采样数据，并将采样数据和所选择的数字样本组成数据集。 一系列数据集可以传送到系统的接收端或存储在记录介质中。 采样数据用于指示数字采样转换为相应模拟值的点。

公开(公告)号：US4568912A

公开(公告)日：1986-02-04

申请号：US475406

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka

IPC: H03M1/00 ,  H04B12/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/3115 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/415 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/648 ,  H03M2201/838

Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum associated with each digital sample is received by a decoder. The sampling datum indicates the sampling interval of the associated digital sample. The decoder includes a microcomputer for storing the digital signal into a memory (M2) and reading each digital sample and the associated sampling datum. The digital sample is divided by the sampling datum to derive a quotient which indicates the slope of the signal to be recovered. The quotient is integrated by an integrator (6b) to provide interpolation between successive sampling points, so that the original signal is approximated by a plurality of line segments.

Abstract translation: 在数据压缩系统中，由解码器接收包括一系列数字样本和与每个数字样本相关联的采样数据的数字信号。 采样数据表示相关数字采样的采样间隔。 解码器包括用于将数字信号存储到存储器（M2）中并读取每个数字样本和相关联的采样数据的微型计算机。 数字样本被采样数据除以导出指示要恢复的信号的斜率的商。 积分器（6b）对商进行积分，以在连续采样点之间提供内插，使原始信号由多个线段近似。

公开(公告)号：US3935569A

公开(公告)日：1976-01-27

申请号：US397924

申请日：1973-09-17

Applicant: Francois Marcel ,  Alain Manoury

Inventor： Francois Marcel ,  Alain Manoury

IPC: H03M1/14 ,  H03M1/00 ,  H03K13/175

CPC classification number: H03M1/00 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2208 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/522 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121

Abstract: The invention concerns a digital coder subject to a compression law having multiple linear segments with slopes decreasing in geometrical progression having a ratio of 1/2, in which a chain of threshold detectors in a linear progression is used a first time to determine the number of the segment, then a second time to determine the position of the level on the segment.

Abstract translation: 本发明涉及经受压缩规律的数字编码器，该数字编码器具有多个线性段，其斜率以1/2的比例在几何级数上减小，其中使用线性进程中的阈值检测器链第一次来确定 该段，然后第二次确定段上的水平位置。

公开(公告)号：KR1020150025571A

公开(公告)日：2015-03-11

申请号：KR1020130103217

申请日：2013-08-29

Applicant: 에스케이하이닉스 주식회사 ,  한국과학기술원

Inventor： 전세준 ,  배현민 ,  이현배

IPC: H03M1/12

CPC classification number: H03M1/182 ,  H03M1/1245 ,  H03M1/34 ,  H03M2201/196 ,  H03M2201/6135

Abstract: 본 발명에 따르면, ADC 기준 레벨을 적응적으로 배치시킴으로써 비트 에러 율을 직접적으로 최적화할 수 있고, 복수의 이퀄라이저 내에 배치된 ADC의 기준전압 레벨을 상호 독립적으로 배치시켜 비트 에러 율을 최적화할 수 있다.
본 발명에 따른 A/D 변환 장치는, 외부로부터 인가되는 외부 클럭을 이용하여 주기가 동일하고, 위상이 서로 다른 제1 클럭과 제2 클럭을 출력하는 클럭 제너레이터; 외부로부터 수신되는 왜곡된 디지털 입력 신호의 반주기 내 제1 및 제2 위상에서 각각 샘플링하여 홀드하는 샘플홀드부; 상기 제1 위상에서 상태를 천이하는 제1 클럭에 동기되어 상기 제1 위상에서 홀드된 제1 홀드 신호를 입력받고, 인가되는 가중치를 이용하여 트랜스미터로부터 출력되는 디지털 신호와 균등화 신호 사이의 에러를 감소시키도록 구성된 제1 입력단 이퀄라이저; 상기 제2 위상에서 상태를 천이하는 제2 클럭에 동기되어 상기 제2 위상에 홀드된 제2 홀드 신호를 입력받고, 상기 가중치를 이용하여 상기 트랜스미터로부터 출력되는 디지털 신호와 상기 균등화 신호 사이의 에러율을 감소시키도록 구성된 제2 입력단 이퀄라이저; 상기 제1 및 제2 입력단 이퀄라이저의 출력을 가산하여 상기 균등화 신호를 생성하고, 상기 트랜스미터로부터 출력되는 디지털 신호에서 상기 균등화 신호를 감산하여 에러 신호를 출력하는 에러 생성부; 및 상기 균등화 신호를 슬라이싱하여 슬라이스드 출력 신호를 생성하는 슬라이서를 포함한다.

Abstract translation: 根据本发明，可以通过自适应地分配用于模数转换器（ADC）的参考电平来直接优化误比特率，并且可以通过将分配在多个均衡器中的ADC的参考电平分配为 彼此独立。 根据本发明的ADC器件包括使用从外部施加的外部时钟以差分相位输出第一和第二时钟的时钟发生器; 采样保持单元，在从外部接收的失真的数字输入信号的半周期内的第一和第二相位进行采样，并保持采样结果; 第一输入级均衡器，被配置为与其状态在第一相位移位的第一时钟同步，接收保持在第一相位的第一保持信号，并且减少从发送器输出的数字信号与均衡之间的误差 通过使用施加的重量信号; 第二输入级均衡器，被配置为与状态在第二相位移位的第二时钟同步，接收保持在第二相位的第二保持信号，并减少从发送器输出的数字信号与均衡之间的误差 通过使用施加的重量信号; 误差产生单元，用于对来自第一和第二级均衡器的输出进行求和以产生均衡信号，并从从发送器输出的数字信号中减去均衡信号以输出误差信号; 以及切片器，其对均衡信号进行切片以产生切片输出信号。

公开(公告)号：KR1020020096006A

公开(公告)日：2002-12-28

申请号：KR1020010034680

申请日：2001-06-19

Applicant: 엘지전자 주식회사

Inventor： 박준한

IPC: H03M1/12

CPC classification number: H03M1/06 ,  H03M2201/196 ,  H03M2201/622

Abstract: PURPOSE: An apparatus and a method for improving a resolution of an input signal in a mobile station modem(MSM) are provided to receive an input signal with a desired resolution since an input signal inputted from an external interface device to the MSM is digital signal processed at a processor without depending on an analog digital(AD) converter in the MSM when the input signal from the external interface device to the MSM is quantized. CONSTITUTION: An apparatus for improving a resolution of an input signal in a mobile station modem(MSM)(130) includes a subtraction block(110) for receiving an input signal from an external interface device and for subtracting the input signal and a feedback signal, an AD converter(131) of the MSM(130) for receiving the output signal of the subtraction block(110) through an integrator(120), a processor(132) for implementing a calculation by receiving the output signal of the AD converter(131) and a feedback terminal(140) for feeding back the control signal of the processor(132) to the subtraction block(110).

Abstract translation: 目的：提供一种用于提高移动台调制解调器（MSM）中的输入信号的分辨率的装置和方法，用于以期望的分辨率接收输入信号，因为从外部接口装置输入到MSM的输入信号是数字信号 在来自外部接口设备到MSM的输入信号被量化时，在处理器处理而不依赖于MSM中的模拟数字（AD）转换器。 一种用于提高移动台调制解调器（MSM）（130）中的输入信号的分辨率的装置，包括：减法块（110），用于从外部接口装置接收输入信号，并减去输入信号和反馈信号 ，用于通过积分器（120）接收减法块（110）的输出信号的MSM（130）的AD转换器（131），用于通过接收AD转换器的输出信号来实现计算的处理器（132） （131）和用于将处理器（132）的控制信号反馈到减法模块（110）的反馈终端（140）。

公开(公告)号：KR1020100067466A

公开(公告)日：2010-06-21

申请号：KR1020080126042

申请日：2008-12-11

Applicant: 삼성전기주식회사

Inventor： 정찬용

IPC: H03M1/12 ,  H03M3/00

CPC classification number: H03M3/402 ,  H03M1/12 ,  H03M3/458 ,  H03M2201/196

Abstract: PURPOSE: A converter and a wireless telecommunications system using the same are provided to possessively process a signal for various frequency signals of inputs by controlling a sampling frequency offered to a sigma-delta modulator according to an analog input signal. CONSTITUTION: A converter(200) includes a band pass, a sigma-delta modulator(210) and a detector(220). The sigma-delta modulator outputs a digital frequency signal by sigma-delta-modulating an analog signal using a received set sampling frequency. The detector senses a band of the analog signal. The detector supplies the sampling frequency to the sigma-delta modulator according to the detected signal. The detector includes a frequency-voltage converter(221) for changing the frequency of the analog signal into the voltage, an analog-digital converter(222) for changing the voltage into the digital signal and a clock control part(223) for adjusting the sampling frequency.

Abstract translation: 目的：通过根据模拟输入信号控制提供给Σ-Δ调制器的采样频率，提供了一种转换器和使用该转换器和无线电信系统来对输入的各种频率信号进行信号处理。 构成：A转换器（200）包括带通，Σ-Δ调制器（210）和检测器（220）。 Σ-Δ调制器通过使用接收的设定采样频率对模拟信号进行Σ-Δ调制来输出数字频率信号。 检测器检测模拟信号的频带。 检测器根据检测到的信号将采样频率提供给Σ-Δ调制器。 检测器包括用于将模拟信号的频率改变为电压的频率 - 电压转换器（221），用于将电压改变为数字信号的模数转换器（222）和用于调整电压的时钟控制部分（223） 采样频率。