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    柔性雷克接收机结构
    31.
    发明公开
    柔性雷克接收机结构 无效

    公开(公告)号：CN1489832A

    公开(公告)日：2004-04-14

    申请号：CN02804245.X

    申请日：2002-11-01

    Applicant: 株式会社东芝

    Inventor： A·C·多尔温

    IPC: H04B1/707

    CPC classification number: H04B1/7113 ,  H04B1/709 ,  H04B1/7115 ,  H04B1/7117 ,  H04B2201/70707 ,  H04B2201/7071 ,  H04B2201/70711

    Abstract: 柔性雷克接收机结构提供了一种雷克接收机处理系统(200)，包括通过多路复用器(232)连接至部分相关器模块(236)的一个输入端的至少两个可编程扩展序列块(224，226)。部分相关器模块的第二输入端与第二多路复用器(234)相连以允许选择多个经延时的IQ采样之一。多个扰码发生器(202)与扰码总线(208)相连并且为每个扩展序列块(224，226)提供相应的多路复用器(220，222)来允许从扰码发生器之一选择输入。多个寄存器(242)允许在处理器(260)的控制下自适应雷克接收机配置。该系统使硬件资源能够按照接收到的信道条件和所需的数据速率而被时分复用并且/或者重新分配。

    改善されたマルチキャリア・スループットのために最適化されたフィンガ割当
    32.
    发明专利
    改善されたマルチキャリア・スループットのために最適化されたフィンガ割当 有权
    用于改进多路径通信的优化指针分配

    公开(公告)号：JP2015159556A

    公开(公告)日：2015-09-03

    申请号：JP2015062460

    申请日：2015-03-25

    Applicant: クゥアルコム・インコーポレイテッド ,  QUALCOMM INCORPORATED

    Inventor： グレゴリー・アール.・リー ,  アブヘイ・エー.・ジョシ ,  ユ−チュアン・ジー.・リン ,  リジュン・リン

    IPC: H04W72/04 ,  H04J11/00 ,  H04B1/16 ,  H04J13/00

    CPC classification number: H04W72/085 ,  H04B1/7117 ,  H04L1/0001 ,  H04L5/0007 ,  H04L5/003 ,  H04L5/006 ,  H04B2201/70711 ,  H04L27/2647

    Abstract: 【課題】広帯域受信機の復調リソースを動的に割り当てることにより、同時に受信された信号の復調を改善するシステムおよび方法を提供する。 【解決手段】指定された信号品質において信号を復調するために、キャリアに関連するどの復調器が、他よりも多くのリソースを必要とするのかを判定するために、複数のキャリアについて、信号対雑音比(SNR)および/またはパケット誤り率(PER)が測定される。関連するキャリアのSNRが高いか、および/または、PERが低い場合、復調器は、関連するキャリアのSNRが低いか、および/または、PERが高い場合よりも、少ないリソースしか必要としない。この点に関して、リソースが、復調器間に動的に割り当てられ、SNR/PERが変化した場合、および/または、追加のリソースが利用可能になった場合、再割当される。 【選択図】図5

    Abstract translation: 要解决的问题：提供动态分配宽带接收机的解调资源的系统和方法，以提供同时接收的信号的改进的解调。解决方案：信噪比（SNR）和/或分组错误率（PER）是 测量多个载波以确定与载波相关的哪些解调器需要比其他载波更多的资源来以指定的信号质量解调信号。 在相关载波的SNR高和/或PER为低的情况下，解调器比相关载波的SNR低和/或PER高的那些需要更少的资源。 在这方面，资源在解调器之间动态分配，并且在SNR / PER改变和/或附加资源可用的情况下被重新分配。

    MULTIPATH DIVERSITY RECEIVING EQUIPMENT OF CDMA SYSTEM
    36.
    发明公开
    MULTIPATH DIVERSITY RECEIVING EQUIPMENT OF CDMA SYSTEM 有权
    MEHRWEGEDIVERSITYEMPFANGSEINRICHTUNGFÜRCDMA系统

    公开(公告)号：EP1840928A4

    公开(公告)日：2010-01-20

    申请号：EP04802551

    申请日：2004-12-28

    Applicant: ZTE CORP

    Inventor： CHEN YUEFENG ,  ZHONG XINCHAO ,  SUN SHAOGANG ,  LIU XINYANG

    IPC: H01J13/00 ,  H04B1/707

    CPC classification number: H04B1/7115 ,  H04B1/71052 ,  H04B1/7117 ,  H04B7/02 ,  H04B2001/70706 ,  H04B2201/70711

    Abstract: The invention provides a multipath diversity receiving equipment of CDMA system, including: a sample quantization device, a sample data storage device, a code data storage device, a mulitpath resource management device, a code resource management device, a demodulation control device, a correlation demodulation device, a channel estimation unit, a energy accumulation device, and a energy analysis processing device. The multipath demodulation, multipath search and delay phase locked loop are all seen as the multipath demodulation, only the energy accumulation should be implemented for multipath phase of the multipath search and delay phase locked loop after the demodulation. The invention combines the multipath demodulation, multipath search and delay phase locked loop together through the hardware, and at the same time with the demodulation control unit , not only realizes the parallel demodulation of multiple multipaths by controlling the correlation demodulation device, but also realizes the operation of the N-dimension matrix, so as to provide the function extension of the combination detection.

    Abstract translation: 本发明提供了一种CDMA系统的多径分集接收设备，包括：采样量化装置，采样数据存储装置，码数据存储装置，多路径资源管理装置，码资源管理装置，解调控制装置，相关 解调装置，信道估计单元，能量积累装置和能量分析处理装置。 多径解调，多路径搜索和延迟锁相环都被视为多路径解调，解调后只能对多路径搜索和延迟锁相环的多径相位实现能量累加。 本发明通过硬件将多径解调，多路径搜索和延迟锁相环组合在一起，同时与解调控制单元相结合，不仅通过控制相关解调装置实现多路径的并行解调，而且实现了 操作N维矩阵，从而提供组合检测的功能扩展。

    METHOD AND APPARATUS FOR JOINT DETECTION
    37.
    发明公开
    METHOD AND APPARATUS FOR JOINT DETECTION 审中-公开
    方法和设备检测复合

    公开(公告)号：EP2080276A2

    公开(公告)日：2009-07-22

    申请号：EP07852443.6

    申请日：2007-09-27

    Applicant: MediaTek Inc.

    Inventor： YAN, Aiguo ,  MARTINOT, Lidwine ,  KOCIC, Marko ,  KRIVACEK, Paul, D. ,  BARBER, Thomas, J., Jr. ,  SHEN, John, Zijun

    IPC: H04B1/707 ,  G06F13/12

    CPC classification number: H04B1/7105 ,  H04B2201/70711

    Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    Data Flow Control
    38.
    发明公开
    Data Flow Control 有权
    Hochgeschwindigkeits-Abwärtsstrecken-Paketzugang（HSDPA）的Datenflusssteuerung

    公开(公告)号：EP2073397A1

    公开(公告)日：2009-06-24

    申请号：EP08171811.6

    申请日：2008-12-16

    Applicant: MediaTek Inc.

    Inventor： Shen, John Zijun ,  Pedersen, Carsten Aagaard ,  Mathew, Deepak ,  Krivacek, Paul D. ,  Yan, Aiguo ,  Fisher-Jeffes, Timothy Perrin

    IPC: H04B1/707

    CPC classification number: H04B1/71055 ,  H04B1/7105 ,  H04B2201/70711 ,  H04J13/0077

    Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.

    Abstract translation: 一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。 该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。 该方法还包括处理第二数据处理模块中的数据用于至少一个信号时隙，以及在完成对第二数据处理模块中的至少一个数据块的处理完成时启用第三数据处理模块，并且确定 第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

    ARCHITECTURE FOR JOINT DETECTION HARDWARE ACCELERATOR
    39.
    发明公开
    ARCHITECTURE FOR JOINT DETECTION HARDWARE ACCELERATOR 有权
    硬件架构的用于多用户检测加速器

    公开(公告)号：EP2067268A2

    公开(公告)日：2009-06-10

    申请号：EP07852447.7

    申请日：2007-09-27

    Applicant: Mediatek Inc.

    Inventor： SHEN, John, Zijun ,  KRIVACEK, Paul, D. ,  BARBER, Thomas, J., Jr. ,  MARTINOT, Lidwine ,  YAN, Aiguo ,  KOCIC, Marko

    IPC: H04B1/707

    CPC classification number: H04B1/7105 ,  H04B2201/70707 ,  H04B2201/70711

    Abstract: A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    MULTIPLE INITIAL SEARCH METHOD FOR CDMA AND GPS SYSTEM
    40.
    发明公开
    MULTIPLE INITIAL SEARCH METHOD FOR CDMA AND GPS SYSTEM 审中-公开
    多重启动搜索程序和CDMA的GPS系统

    公开(公告)号：EP1470653A1

    公开(公告)日：2004-10-27

    申请号：EP03729324.8

    申请日：2003-01-03

    Applicant: Qualcomm, Incorporated

    Inventor： POON, Wang, Paul ,  ZOU, Qiuzhen

    IPC: H04B1/707

    CPC classification number: H04B1/708 ,  G01S19/30 ,  G01S19/34 ,  G01S19/37 ,  H04B1/70754 ,  H04B1/70758 ,  H04B2201/70711

    Abstract: Searcher hardware is multiplexed to perform simultaneous searches in either an IS-95 CDMA mode or a GPS mode. In the IS-95 mode, the search hardware is time-multiplexed into a number of searcher time slices, each of which can generate a PN sequence to despread a data sequence. In the GPS mode, the search hardware is configured as a number of distinct GPS channels, each of which can generate a Gold code sequence for tracking a GPS signal from a particular GPS satellite. This configuration allows the searcher to perform multiple GPS signal searches simultaneously. Signal searching in both IS-95 and GPS modes is performed at significantly higher speeds compared to conventional searcher hardware. Moreover, the search hardware can be dynamically configured to operate in either the IS-95 or the GPS mode, eliminating the need for dedicated circuitry for each mode of operation.

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