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    Method and apparatus for multi-slot power control of wireless transmission
    1.
    发明公开
    Method and apparatus for multi-slot power control of wireless transmission 有权
    用于无线传输多时隙功率控制方法和装置

    公开(公告)号：EP2043401A3

    公开(公告)日：2013-12-04

    申请号：EP08165271.1

    申请日：2008-09-26

    Applicant: MediaTek Inc.

    Inventor： Yan, Aiguo ,  Strange, Jonathan Richard ,  Tenbroek, Bernard ,  Mathew, Deepak ,  Ma, Liang

    IPC: H04W52/04 ,  H04W52/52 ,  H04W52/14

    CPC classification number: H04W52/52 ,  H04W52/04 ,  H04W52/14 ,  H04W52/146

    Abstract: Methods and apparatus are provided for controlling transmitted power in a wireless system. The method includes generating information to be transmitted as a series of signal bursts, with a time interval between successive signal bursts, controlling individually a power level of each of said signal bursts with a power control signal to provide output signal bursts to be transmitted, and asserting a new power value of the power control signal during the time interval preceding each signal burst. The wireless system can be a TDSCDMA wireless system, and the signal bursts can be uplink signal bursts.

    Abstract translation: 提供了方法和装置，用于在无线系统中控制反mitted功率，该方法包括生成信息是反式mitted为一系列的信号突发的，具有连续的信号脉冲串之间的时间间隔，控制与每个所述信号脉冲串中的独立的功率电平 功率控制信号，以提供输出信号突发是反式mitted，以及时间间隔preceding-每一信号突发期间断言所述功率控制信号的新功率值。 该无线系统可以是一个无线TDSCDMA系统，以及信号突发可以是上行链路信号突发。

    TD-SCDMA uplink processing
    2.
    发明公开
    TD-SCDMA uplink processing 审中-公开
    TD-SCDMA上行-Verarbeitung

    公开(公告)号：EP2075920A2

    公开(公告)日：2009-07-01

    申请号：EP08169999.3

    申请日：2008-11-26

    Applicant: Mediatek Inc.

    Inventor： Mathew, Deepak ,  Mestechkin, Russ ,  Ponnathota, Prahallada ,  Howe, Thomas F. ,  Fisher-Jeffes, Timothy Perrin

    IPC: H04B1/707

    CPC classification number: H04B1/707 ,  G06F5/16 ,  G11C7/1075 ,  H04B2201/70707

    Abstract: A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.

    Abstract translation: 无线设备具有BRP-CRP接口，其包括具有第一接入端口和第二接入端口的双端口帧存储器，其中可以通过第一接入端口将数据写入双端口帧存储器，同时该 通过第二个访问端口从双端口帧存储器中读取数据。 比特率处理器对输入数据执行比特率处理，并通过第一接入端口将从比特率处理产生的数据写入双端口帧存储器。 芯片速率处理器通过第二访问端口从双端口帧存储器读取数据，并对从双端口帧存储器读取的数据执行码片速率处理。 数据处理器执行通过第一访问端口将数据写入双端口帧存储器的软件应用程序，并通过第二访问端口从双端口帧存储器读取数据。

    Parameter estimation for modulated signals
    3.
    发明公开
    Parameter estimation for modulated signals 有权
    Parameterbeurteilungfürmodulierte Signale

    公开(公告)号：EP2073476A2

    公开(公告)日：2009-06-24

    申请号：EP08172171.4

    申请日：2008-12-18

    Applicant: MediaTek Inc.

    Inventor： Pedersen, Carsten Aagaard ,  Shen, John Zijun ,  Yan, Aiguo ,  Mathew, Deepak ,  Kocic, Marko ,  Fisher-Jeffes, Timothy Perrin ,  Keller, Thomas

    IPC: H04L27/34

    CPC classification number: H04L27/34 ,  H04L27/3809

    Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.

    Abstract translation: 系统包括用于接收调制信号的接收机。 接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。 增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。 增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。

    TD-SCDMA uplink processing
    6.
    发明公开
    TD-SCDMA uplink processing 审中-公开
    TD-SCDMA上行链路处理

    公开(公告)号：EP2073396A3

    公开(公告)日：2011-06-08

    申请号：EP08169998.5

    申请日：2008-11-26

    Applicant: Mediatek Inc.

    Inventor： Mestechkin, Russ ,  Mathew, Deepak ,  Wang, Justin ,  Nandipaku, Sanjay

    IPC: H04B1/707

    CPC classification number: H04B1/707 ,  H04B2201/70707

    Abstract: A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set oftime slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.

    Abstract translation: 无线系统具有上行链路码片速率处理架构，其中提供至少两组寄存器，每组寄存器存储一组时隙配置参数。 存储器存储一系列时隙配置集标识符，每个时标配置集标识符标识一组寄存器，每个标识符对应于一个时隙。 码片速率处理单元处理多个时隙中的数据流，其中在每个时隙处，并且码片速率处理单元根据存储在与该时隙相关联的寄存器组中的时隙配置参数组来配置 时隙对应的时隙配置集标识。

    TD-SCDMA uplink processing
    8.
    发明公开
    TD-SCDMA uplink processing 审中-公开
    TD-SCDMA上行链路处理

    公开(公告)号：EP2075920A3

    公开(公告)日：2011-05-04

    申请号：EP08169999.3

    申请日：2008-11-26

    Applicant: Mediatek Inc.

    Inventor： Mathew, Deepak ,  Mestechkin, Russ ,  Ponnathota, Prahallada ,  Howe, Thomas F. ,  Fisher-Jeffes, Timothy Perrin

    IPC: H04B1/707 ,  G11C7/10

    CPC classification number: H04B1/707 ,  G06F5/16 ,  G11C7/1075 ,  H04B2201/70707

    Abstract: A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.

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