公开(公告)号：EP2073397B1

公开(公告)日：2017-02-15

申请号：EP08171811.6

申请日：2008-12-16

Applicant: MediaTek Inc.

Inventor： Shen, John Zijun ,  Pedersen, Carsten Aagaard ,  Mathew, Deepak ,  Krivacek, Paul D. ,  Yan, Aiguo ,  Fisher-Jeffes, Timothy Perrin

IPC: H04B1/7105 ,  H04J13/00

CPC classification number: H04B1/71055 ,  H04B1/7105 ,  H04B2201/70711 ,  H04J13/0077

公开(公告)号：EP2251792B1

公开(公告)日：2013-02-20

申请号：EP10174359.9

申请日：2007-09-27

Applicant: MediaTek Inc.

Inventor： Garg, Sachin ,  Krivacek, Paul D.

IPC: G06F15/17

CPC classification number: G06F13/126 ,  G06F9/3881 ,  G06F13/4273 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one aspect, an interface adapted to transfer data between a host processor and an external coprocessor is provided. The interface may be adapted to operate in a plurality of write modes, wherein in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. In another aspect, the interface is adapted to perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. In another aspect, the interface includes a plurality of buffers to store read and write operations and a plurality of clock gates to selectively gate of clock signals provided to the plurality of buffers to synchronize transfer of data into and out of the buffers. In another aspect, the interface includes a selectable priority scheme capable of being modified to select between a plurality of priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.

公开(公告)号：EP2081298A2

公开(公告)日：2009-07-22

申请号：EP08171814.0

申请日：2008-12-16

Applicant: MediaTek Inc.

Inventor： Pedersen, Carsten Aagaard ,  Shen, John Zijun ,  Yan, Aiguo ,  Mathew, Deepak ,  Kocic, Marko ,  Fisher-Jeffes, Timothy Perrin ,  Keller, Thomas ,  Aardoom, Eric ,  Ivory, David Stephen ,  Krivacek, Paul D.

IPC: H04B1/06 ,  H04L25/06 ,  G06F15/78 ,  H03M13/00

CPC classification number: G06F15/7842 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/1829

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Abstract translation: 一种用于在无线系统中处理信号的装置包括：第一存储器模块，用于从一组物理信道接收输入数据;第一多个子模块，用于处理输入数据。 选择第一组多个子模块中的每一个以基于数据和传输信道规范起作用。 该设备还包括第二存储器模块以接收经处理的输入数据并输出中间数据。 第二个存储器中输入数据的位置根据数据和传输通道规格进行分配。 该装置还包括用于处理中间数据的第二多个子模块。 选择第二多个子模块中的每一个以基于数据和传输信道规范起作用。 该设备还包括第三存储器模块以接收和输出比特率处理输出。

公开(公告)号：EP2073397A1

公开(公告)日：2009-06-24

申请号：EP08171811.6

申请日：2008-12-16

Applicant: MediaTek Inc.

Inventor： Shen, John Zijun ,  Pedersen, Carsten Aagaard ,  Mathew, Deepak ,  Krivacek, Paul D. ,  Yan, Aiguo ,  Fisher-Jeffes, Timothy Perrin

IPC: H04B1/707

CPC classification number: H04B1/71055 ,  H04B1/7105 ,  H04B2201/70711 ,  H04J13/0077

Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.

Abstract translation: 一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。 该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。 该方法还包括处理第二数据处理模块中的数据用于至少一个信号时隙，以及在完成对第二数据处理模块中的至少一个数据块的处理完成时启用第三数据处理模块，并且确定 第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

公开(公告)号：EP2251792A1

公开(公告)日：2010-11-17

申请号：EP10174359.9

申请日：2007-09-27

Applicant: Mediatek Inc.

Inventor： Garg, Sachin ,  Krivacek, Paul D.

IPC: G06F15/17

CPC classification number: G06F13/126 ,  G06F9/3881 ,  G06F13/4273 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one aspect, an interface adapted to transfer data between a host processor and an external coprocessor is provided. The interface may be adapted to operate in a plurality of write modes, wherein in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. In another aspect, the interface is adapted to perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. In another aspect, the interface includes a plurality of buffers to store read and write operations and a plurality of clock gates to selectively gate of clock signals provided to the plurality of buffers to synchronize transfer of data into and out of the buffers. In another aspect, the interface includes a selectable priority scheme capable of being modified to select between a plurality of priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.

Abstract translation: 在一个方面中，接口angepasst到主机处理器之间，并外协处理器提供传输数据。 所述接口可以被angepasst在写入模式的多元性进行操作，在第一写模式的写手术是在两个时钟周期，并且在第二写入模式下写入手术是在一个单一的时钟跨越接口传输跨越接口传输worin 周期。 在另一个方面，该接口是angepasst执行第一读取操作由主机处理器发起和第二读取操作由外协处理器发起。 在另一个方面，所述接口包括缓冲器来存储读写操作的多个部分并加以时钟门提供给缓冲器的多元性同步传送数据的流入和流出缓冲器的时钟信号的选择性栅极复数。 在另一个方面，所述接口包括能够被修改优先级之间的多个选择的可选择的优先级方案做了控制传递环的操作通过接口偏好当读取和写入操作被排队等待传输。

公开(公告)号：EP2081298A3

公开(公告)日：2009-07-29

申请号：EP08171814.0

申请日：2008-12-16

Applicant: MediaTek Inc.

Inventor： Pedersen, Carsten Aagaard ,  Shen, John Zijun ,  Yan, Aiguo ,  Mathew, Deepak ,  Kocic, Marko ,  Fisher-Jeffes, Timothy Perrin ,  Keller, Thomas ,  Aardoom, Eric ,  Ivory, David Stephen ,  Krivacek, Paul D.

IPC: H04B1/06 ,  H04L25/06 ,  G06F15/78 ,  H03M13/00

CPC classification number: G06F15/7842 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/1829

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.