公开(公告)号：WO2012075306A2

公开(公告)日：2012-06-07

申请号：PCT/US2011/062914

申请日：2011-12-01

Applicant: 1366 TECHNOLOGIES INC. ,  JONCZYK, Ralf ,  SACHS, Emanuel, M.

Inventor： JONCZYK, Ralf ,  SACHS, Emanuel, M.

IPC: H01L21/28

CPC classification number: H01L31/182 ,  C04B41/4539 ,  C04B41/5096 ,  C30B11/002 ,  C30B15/00 ,  C30B15/007 ,  C30B15/32 ,  C30B29/06 ,  H01L21/02002 ,  H01L21/02532 ,  H01L31/1804 ,  Y02E10/546 ,  Y02P70/521

Abstract: An interposer sheet can be used for making semiconductor bodies, such as of silicon, such as for solar cell use. It is free-standing, very thin, flexible, porous and able to withstand the chemical and thermal environment of molten semiconductor without degradation. It is typically of a ceramic material, such as silica, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride and others. It is provided between a forming surface of a mold sheet, and the molten material from which a semiconductor body will be formed. It may be secured to the forming surface or deposited upon the melt. The interposer sheet suppresses grain nucleation, and limits heat flow from the melt. It promotes separation of the semiconductor body from the forming surface. It can be fabricated before its use. Because free-standing and not adhered to the forming surface, problems of mismatch of CTE are minimized. The interposer sheet and semiconductor body are free to expand and contract relatively independently of the forming surface.

Abstract translation: 插入片可用于制造诸如硅的半导体本体，例如用于太阳能电池。 它是独立的，非常薄的，柔性的，多孔的并且能够耐受熔融半导体的化学和热环境而不降解。 它通常是陶瓷材料，例如二氧化硅，氮化硅，氮氧化硅，碳氧化硅，碳化硅，碳氮化硅，碳氮氧化硅等。 设置在模板的成形表面和将形成半导体本体的熔融材料之间。 它可以固定到成形表面或沉积在熔体上。 插入片抑制晶粒成核，并限制来自熔体的热流。 它促进半导体主体与成形表面的分离。 它可以在使用之前进行制造。 由于独立且不粘附到成型表面，CTE的失配问题被最小化。 插入片和半导体本体相对于成形表面相对自由地膨胀和收缩。

公开(公告)号：WO2010129884A1

公开(公告)日：2010-11-11

申请号：PCT/US2010/034067

申请日：2010-05-07

Applicant: 1366 TECHNOLOGIES INC. ,  SACHS, Emanuel, M. ,  GABOR, Andrew, M.

Inventor： SACHS, Emanuel, M. ,  GABOR, Andrew, M.

IPC: H01L21/306 ,  H01L31/00 ,  H01L31/18

CPC classification number: H01L31/022425 ,  H01L21/76802 ,  H01L31/02363 ,  H01L31/18 ,  Y02E10/50

Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A film is applied over a patterned porous layer, the layer comprising openings typically larger than the film thickness. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities where the film does not bridge the spaces between solid portions, so that the etchant attacks both film surfaces

Abstract translation: 多孔提升层有助于从诸如半导体的表面去除膜。 将膜施加在图案化的多孔层上，该层包括通常大于膜厚度的开口。 然后将多孔材料和膜从不需要膜的区域中取出。 多孔层可以作为浆料提供，干燥以打开孔隙，或场内的逸散颗粒，其在施加热或溶剂时解离。 可以通过蚀刻剂从薄膜不固定部分之间的空隙的孔隙中进入薄膜，从而使蚀刻剂侵袭两个薄膜表面

公开(公告)号：WO2021188452A1

公开(公告)日：2021-09-23

申请号：PCT/US2021/022402

申请日：2021-03-15

Applicant: 1366 TECHNOLOGIES, INC.

Inventor： JONCZYK, Ralf ,  MCMAHON, Patrick

IPC: H01L31/0236 ,  H01L31/18 ,  H01L31/182

Abstract: A method includes etching silicon using a mixture of nitric acid and hydrofluoric acid in which less than 6 mols of hydrofluoric acid is used to etch one mol of silicon. The etching may be conducted at an elevated temperature, such as a temperature of at least 70 degrees Celsius.

公开(公告)号：WO2012075306A3

公开(公告)日：2013-07-25

申请号：PCT/US2011062914

申请日：2011-12-01

Applicant: 1366 TECHNOLOGIES INC ,  JONCZYK RALF ,  SACHS EMANUEL M

Inventor： JONCZYK RALF ,  SACHS EMANUEL M

IPC: H01L21/02 ,  C30B19/02

CPC classification number: H01L31/182 ,  C04B41/4539 ,  C04B41/5096 ,  C30B11/002 ,  C30B15/00 ,  C30B15/007 ,  C30B15/32 ,  C30B29/06 ,  H01L21/02002 ,  H01L21/02532 ,  H01L31/1804 ,  Y02E10/546 ,  Y02P70/521

Abstract: Interposer sheet for making silicon solar semiconductor bodies. Interposer is free-standing, thin, flexible, porous and withstands chemical/thermal environment of molten semiconductor without degradation. Interposer is of ceramic material, such as silica, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride and others. Provided between a forming surface of a mold sheet, and the molten material from which a semiconductor body will be formed. Secured to the forming surface or deposited upon the melt. Interposer suppresses grain nucleation, and limits heat flow from the melt, promotes separation of the semiconductor body from the forming surface, prefabricated before use. Because free-standing and not adhered to the forming surface, problems of mismatch of CTE are minimized. Interposer and semiconductor body are free to expand and contract relatively independently of the forming surface.

Abstract translation: 制造硅太阳能半导体器件的插入片。 中间层是独立的，薄的，柔性的，多孔的并且耐受熔融半导体的化学/热环境而不降解。 中间体是陶瓷材料，例如二氧化硅，氮化硅，氮氧化硅，碳氧化硅，碳化硅，碳氮化硅，碳氮氧化硅等。 在模板的成形表面和将形成半导体本体的熔融材料之间。 固定在成型表面上或沉积在熔体上。 中间层抑制晶粒成核，并限制来自熔体的热流，促进半导体本体与成形表面的分离，在使用前预制。 由于独立且不粘附到成型表面，CTE的失配问题被最小化。 内插器和半导体主体可以独立于成形表面自由地膨胀和收缩。

公开(公告)号：WO2013103930A2

公开(公告)日：2013-07-11

申请号：PCT/US2013/020435

申请日：2013-01-06

Applicant: 1366 TECHNOLOGIES, INC.

Inventor： TARASOV, Vladimir ,  ERSEN, Ali ,  STERN, Eric ,  CRISCIONE, Jason, M. ,  SACHS, Emanuel, M.

IPC: H01L21/3063

CPC classification number: H01L31/02363 ,  H01L31/0248 ,  Y02E10/50

Abstract: Processes increase light absorption into silicon wafers by selectively changing the reflective properties of the bottom portions of light trapping cavity features. Modification of light trapping features includes: deepening the bottom portion, increasing the curvature of the bottom portion, and roughening the bottom portion, all accomplished through etching. Modification may also be by the selective addition of material at the bottom of cavity features. Different types of features in the same wafers may be treated differently. Some may receive a treatment that improves light trapping while another is deliberately excluded from such treatment. Some may be deepened, some roughened, some both. No alignment is needed to achieve this selectively. The masking step achieves self-alignment to previously created light trapping features due to softening and deformation in place.

Abstract translation: 通过选择性地改变光阱特征的底部的反射特性，工艺增加了对硅晶片的光吸收。 光捕获特征的改进包括：深化底部部分，增加底部部分的曲率，以及粗糙化底部部分，全部通过蚀刻来实现。 修改也可以通过在腔体特征的底部选择性地添加材料。 不同类型的相同晶片中的特征可以被不同地对待。 有些可能会接受改善光线捕获的治疗方法，而另一种方法被故意排除在这种治疗之外。 有些可能会加深，有些粗糙，有的两个。 不需要对准以选择性地实现。 掩蔽步骤由于在现场的软化和变形而实现了先前产生的光捕获特征的自对准。

公开(公告)号：WO2012094169A2

公开(公告)日：2012-07-12

申请号：PCT/US2011/066842

申请日：2011-12-22

Applicant: 1366 TECHNOLOGIES INC. ,  SACHS, Emanuel, M. ,  SERDY, James, G.

Inventor： SACHS, Emanuel, M. ,  SERDY, James, G.

IPC: B32B5/26

CPC classification number: C30B15/007 ,  C30B29/06

Abstract: A string for growing ribbon crystal has a core and an outer cover, the cover composed of at least two different materials, chosen with the material of the core in amount and kind such that the CTE of the covered core matches in net, that of the silicon ribbon. The cover material is also chosen so that silicon readily wets significantly around the string, subtending an angle of at least about 55 degrees, up to a fully wetted string, resulting in a relatively thick strong ribbon adjacent the string, closer in thickness to the diameter of the sting. This prevents a thin, fragile ribbon near the string. For silicon ribbon, a cover may be an interspersed composition that is predominantly of silica, with some SiC. The core may also be composed of silica and SiC, in different proportions, and different geometry. Or, the core may be a single material, such as Carbon. SiC present in the cover in an amount as low as 10% by volume permits wetting around at least about 55 degrees of string circumference and does not excessively nucleate grain growth. Higher amounts of SiC are also beneficial. Using these same, or similar materials, the outer cover can be made fully dense and free of impurities that would harm silicon. The cover can be electrically non-conductive. Rather than silicon carbide, silicon nitride, and other materials can be used. It is also possible to intentionally mismatch the CTE of the string and the ribbon, such that the ribbon is in compression at the ends of the strings, which helps to prevent ribbon fracture.

Abstract translation: 用于生长的带状晶体的线条具有芯部和外部覆盖物，所述覆盖物由至少两种不同的材料组成，其选择的材料的数量和种类的核心的材料使得被覆盖的芯部的CTE在网中匹配， 硅带。 覆盖材料也被选择成使得硅很容易在弦的周围润湿，对角至少约55度的角度，直到完全润湿的线，导致邻近弦的相对厚的强带，其厚度更接近于直径 的刺痛。 这样可以防止弦附近的薄而脆弱的丝带。 对于硅带，覆盖物可以是散在的组合物，其主要是二氧化硅，具有一些SiC。 核心也可以由不同比例的二氧化硅和SiC组成，并且具有不同的几何形状。 或者，核心可以是单一材料，例如碳。 存在于覆盖物中的低至10体积％的量的SiC允许在至少约55度的串周长处润湿，并且不会使晶粒生长过度成核。 更高量的SiC也是有益的。 使用这些相同或相似的材料，外盖可以制成完全致密且没有会损害硅的杂质。 盖可以是非导电的。 可以使用碳化硅，氮化硅等材料。 还可以有意地使串和色带的CTE不匹配，使得色带在色带的端部处被压缩，这有助于防止色带断裂。

公开(公告)号：WO2009145857A1

公开(公告)日：2009-12-03

申请号：PCT/US2009/002422

申请日：2009-04-17

Applicant: 1366 TECHNOLOGIES INC. ,  GABOR, Andrew, M ,  WALLACE, Richard, L.

Inventor： GABOR, Andrew, M ,  WALLACE, Richard, L.

IPC: H01L31/00

CPC classification number: H01L31/1804 ,  H01L21/228 ,  H01L21/6715 ,  H01L31/022425 ,  H01L31/0288 ,  Y02E10/547 ,  Y02P70/521

Abstract: Methods exploiting a Self Aligned Cell (SAC) architecture for doping purposes, use the architecture to direct the deposition and application of either a dopant or a diffusion retarder. Doping is provided in regions that will become metallization for conducting fingers. Dopant may be treated directly into metallization grooves. Or, diffusion retarder may be provided in non-groove locations, and dopant may be provided over some or all of the entire wafer surface. Dopant and metal automatically go where desired, and in register with each other. The SAC architecture also includes concave surfaces for light absorbing regions of a cell, to reduce reflection of light energy, which regions may also be treated with dopant in the concavities, to result in semiconductor emitter lines. Alternatively, diffusion retarder may be treated into the concavities, leaving upper tips of ridges between the concavities exposed, thereby subject to deeper doping.

Abstract translation: 利用自对准单元（SAC）架构进行掺杂的方法，使用该架构来指导掺杂剂或扩散延迟器的沉积和应用。 在将成为导电手指的金属化的区域中提供掺杂。 掺杂剂可以直接处理成金属化槽。 或者，扩散延迟器可以设置在非凹槽位置，并且可以在整个晶片表面的一些或全部上提供掺杂剂。 掺杂剂和金属自动进入需要的地方，并相互注册。 SAC架构还包括用于单元的光吸收区域的凹面，以减少光能的反射，哪些区域也可以在凹部中用掺杂剂处理，以产生半导体发射线。 或者，扩散延迟器可以被处理成凹面，从而使暴露的凹部之间的脊的上部尖端留下更深的掺杂。

公开(公告)号：WO2009128946A1

公开(公告)日：2009-10-22

申请号：PCT/US2009/002423

申请日：2009-04-17

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  1366 TECHNOLOGIES INC. ,  POLITO, Benjamin, E. ,  GATES, Holly, G. ,  SACHS, Emanuel, M.

Inventor： POLITO, Benjamin, E. ,  GATES, Holly, G. ,  SACHS, Emanuel, M.

IPC: B29C59/02

CPC classification number: H01L31/182 ,  B29C43/021 ,  B29C43/222 ,  B29C59/02 ,  B29C2043/025 ,  B29C2043/3634 ,  B29C2043/3652 ,  B29C2043/465 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L31/0236 ,  H01L31/02363 ,  Y02E10/50

Abstract: Patterned substrates for photovoltaic and other uses are made by pressing a flexible stamp upon a thin layer of resist material, which covers a substrate, such as a wafer. The resist changes phase or becomes flowable, flowing away from locations of impression, revealing the substrate, which is subjected to some shaping process, typically etching. Portions exposed by the stamp being are removed, and portions that protected by the resist, remain. A typical substrate is silicon, and a typical resist is a wax. Workpiece textures include extended grooves, discrete, spaced apart pits, and combinations and intermediates thereof. Platen or rotary patterning apparatus may be used. Rough and irregular workpiece substrates may be accommodated by extended stamp elements. Resist may be applied first to the workpiece, the stamp, or substantially simultaneously, in discrete locations, or over the entire surface of either. The resist dewets the substrate completely where desired.

Abstract translation: 用于光伏和其他用途的图案化基板是通过将柔性印模压在覆盖诸如晶片的基底的抗蚀剂材料薄层上而制成的。 抗蚀剂改变相位或变得可流动，从印模的位置流出，露出经受一些成形过程的基底，通常是蚀刻。 被邮票曝光的部分被去除，并且被抗蚀剂保护的部分保留。 典型的基底是硅，典型的抗蚀剂是蜡。 工件纹理包括延伸凹槽，离散的，间隔开的凹坑，以及它们的组合和中间体。 可以使用压板或旋转图案形成装置。 粗糙和不规则的工件衬底可以由延长的印模元件容纳。 抗蚀剂可以首先施加到工件，印模或基本上同时地在离散的位置，或者在两者的整个表面上。 抗蚀剂在需要时完全将基材脱模。

公开(公告)号：TWI667700B

公开(公告)日：2019-08-01

申请号：TW100144314

申请日：2011-12-01

Applicant: 美商1366科技公司 ,  1366 TECHNOLOGIES INC.

Inventor： 裘賽克 瑞芙 ,  JONCZYK, RALF ,  莎栩思 伊繆爾M ,  SACHS, EMANUEL M.

IPC: H01L21/30 ,  H01L31/068

公开(公告)号：TW201628211A

公开(公告)日：2016-08-01

申请号：TW104138228

申请日：2015-11-19

Applicant: 1366科技公司 ,  1366 TECHNOLOGIES, INC.

Inventor： 強克席克 拉爾夫 ,  JONCZYK, RALF ,  卡能 布萊恩D ,  KERNAN, BRIAN D. ,  胡德森 斯蒂芬G D ,  HUDELSON, STEPHEN G. D. ,  羅倫茲 亞當M ,  LORENZ, ADAM M. ,  莎栩思 伊繆爾M ,  SACHS, EMANUEL M.

IPC: H01L31/18 ,  H01L29/36 ,  H01L31/0248

CPC classification number: H01L31/1804 ,  H01L21/00 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/0288 ,  H01L31/056 ,  H01L31/068 ,  Y02E10/52 ,  Y02E10/547 ,  Y02P70/521

Abstract: 本發明提供一種半導體晶圓，其形成在一含有摻雜物的模具之上。該摻雜物會摻雜相鄰於該模具的熔融物區域。該處的摻雜物濃度高於該熔融物本體。一晶圓會開始凝固。摻雜物在固體半導體之中的擴散效果不佳。在一晶圓開始凝固之後，摻雜物便無法進入該熔融物。而後，在相鄰於該晶圓表面的熔融物之中的摻雜物的濃度會小於出現在該晶圓開始形成的地方的摻雜物的濃度。新的晶圓區域會隨著時間經過而從摻雜物濃度變低的熔融物區域處成長。這會在該晶圓之中建立一摻雜物梯度，較高的濃度相鄰於該模具。該梯度能夠被修正。梯度會導致一電場，其能夠發揮漂移電場或背表面電場的功能。太陽能收集器在該背表面處會具有多個開放格柵的導體並且具有較佳的光學反射器，其可由該本質背表面電場來達成。

Abstract in simplified Chinese: 本发明提供一种半导体晶圆，其形成在一含有掺杂物的模具之上。该掺杂物会掺杂相邻于该模具的熔融物区域。该处的掺杂物浓度高于该熔融物本体。一晶圆会开始凝固。掺杂物在固体半导体之中的扩散效果不佳。在一晶圆开始凝固之后，掺杂物便无法进入该熔融物。而后，在相邻于该晶圆表面的熔融物之中的掺杂物的浓度会小于出现在该晶圆开始形成的地方的掺杂物的浓度。新的晶圆区域会随着时间经过而从掺杂物浓度变低的熔融物区域处成长。这会在该晶圆之中创建一掺杂物梯度，较高的浓度相邻于该模具。该梯度能够被修正。梯度会导致一电场，其能够发挥漂移电场或背表面电场的功能。太阳能收集器在该背表面处会具有多个开放格栅的导体并且具有较佳的光学反射器，其可由该本质背表面电场来达成。