公开(公告)号：US20190139457A1

公开(公告)日：2019-05-09

申请号：US16129344

申请日：2018-09-12

Applicant: SOLUTION 3D PLUS INC.

Inventor： Michel Cournoyer

IPC: G09F3/02 ,  F16B1/00

Abstract: The present invention relates to label, device, system and method for sorting bolts, bars, pins, studs, dowels, screws or the like (collectively and individually described herein as a bolt). The bolts are being characterized by a first and a second dimension. The identification system comprises a color chart defining all ten numerals and most commonly used bolt diameters corresponding to various colors and an identification label. The identification label comprises a main section and at least one other section being both adapted to receive at least one color and/or a numeral. Each combination of a color and a numeral being defined by the color chart. The combination of colors and/or numerals of the main section defines the first dimension of the bolt and the combination of colors and/or numerals of the at least one other section defines the second dimension of the bolt.

公开(公告)号：US20190103380A1

公开(公告)日：2019-04-04

申请号：US16077968

申请日：2017-02-14

Applicant: 3D PLUS

Inventor： Christian VAL

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/16 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/16 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: A 3D electronic module including, in a direction referred to as the vertical direction, a stack of electronic dice, each die including at least one chip provided with interconnect pads, this stack being attached to an interconnect circuit for the module provided with connection bumps, the pads of each chip being connected by electrical bonding wires to vertical buses that are themselves electrically linked to the interconnect circuit for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, wherein each electrical bonding wire is linked to its vertical bus by forming, in a vertical plane, an oblique angle and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another die and the corresponding vertical bus, and this is obtained by wiring the bonding wire in a non-rectilinear manner to compensate for the difference in vertical length of the vertical bus from one die to the other, such that the electrical conductor between the pad of a chip of one die and the interconnect circuit, and the electrical conductor between the same pad of a chip of the other die and the interconnect circuit, are the same length.

公开(公告)号：US09899250B2

公开(公告)日：2018-02-20

申请号：US15621908

申请日：2017-06-13

Applicant: 3D PLUS

Inventor： Christian Val

IPC: H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H05K3/32

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/142 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K3/321 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages, several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers, dicing of the stacked reconstituted wafers to obtain 3D modules.

公开(公告)号：WO2019158585A1

公开(公告)日：2019-08-22

申请号：PCT/EP2019/053548

申请日：2019-02-13

Applicant: 3D PLUS

Inventor： VAL, Christian

IPC: C23C18/16 ,  H05K3/18 ,  C23C18/32 ,  C23C18/38

Abstract: L'invention concerne un procédé de dépôt en phase liquide de couches métalliques dans des trous (11) d'un module électronique (10) disposé dans une enceinte hermétique (1), à partir d'un liquide (4) chimique à composés métalliques destinés à former une couche métallique. Les trous ont une profondeur P et un diamètre D tels que D>80 µm et P/D > 10, et le procédé comporte au moins un cycle (Cyc) comportant les sous-étapes suivantes : - M1) Mise sous une pression prédéterminée P0 de l'enceinte et remplissage de l'enceinte par le liquide, - M2) Dégazage des trous par mise sous une pression réduite P1 de l'enceinte, avec P1

公开(公告)号：WO2012152672A2

公开(公告)日：2012-11-15

申请号：PCT/EP2012/058195

申请日：2012-05-04

Applicant: 3D PLUS ,  VAL, Christian

Inventor： VAL, Christian

IPC: H01L23/538 ,  H01L21/60 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01G4/224 ,  B05D1/02 ,  B05D5/10 ,  C23C14/08 ,  C23C16/01 ,  C23C16/402 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/18 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: L'invention concerne un procédé de fabrication collective d'une plaque reconstituée qui comporte des puces présentant des plots de connexion sur une face de la puce dite face avant, qui comprend une étape de : A) positionnement des puces sur un support adhésif initial, face avant sur le support, caractérisé en ce qu'il comprend les étapes suivantes : B) dépôt en phase gazeuse à la pression atmosphérique et à la température ambiante, d'une couche électriquement isolante sur le support initial et les puces, cette couche ayant un rôle mécanique de maintien des puces, C) transfert des puces recouvertes de la couche minérale sur un support adhésif provisoire, face arrière des puces vers ce support adhésif provisoire, D) retrait du support adhésif initial, E) report des puces sur un support de type « chuck », faces avant des puces vers ce support, F) retrait du support adhésif provisoire, G) dépôt d'une résine sur le support de type « chuck » pour encapsuler les puces, puis polymérisation de la résine, H) retrait du support de type « chuck », I) réalisation d'une couche RDL côté face active

Abstract translation: 本发明涉及一种用于集体生产重构晶片的方法，该方法包括在所述芯片的所谓正面上具有连接焊盘的芯片，所述方法包括以下步骤：A）将芯片放置在初始粘合剂载体上，前面 其特征在于其包括以下步骤：B）在大气压和室温的气相中沉积初始载体和芯片上的电绝缘层，该层在支撑中具有机械作用 芯片; C）将覆盖有矿物层的碎片转移到临时粘合剂载体上，芯片的后侧面向临时粘合剂载体; D）去除初始粘合剂载体; E）将芯片放置在卡盘上，芯片的前侧面向卡盘; F）去除临时粘合剂载体; G）将树脂沉积在卡盘上以封装芯片，然后固化树脂; H）取出卡盘; 和I）在活动侧产生RDL。

公开(公告)号：TW201709440A

公开(公告)日：2017-03-01

申请号：TW105120001

申请日：2016-06-24

Applicant: 3D波拉斯公司 ,  3D PLUS

Inventor： 佛 克里斯汀 ,  VAL, CHRISTIAN

IPC: H01L23/31 ,  H01L23/48

CPC classification number: H05K1/18 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5387 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/00 ,  H01L25/105 ,  H05K1/147 ,  H05K1/189

Abstract: 本發明關於一種3D電子模組(100)，其包含：- 兩個經電性測試的電子封裝(10)，各包含至少一封裝晶片(11)與輸出球(13)於該封裝的一單一面上，該單一面稱為該主要面(15)；- 彼此機械性連接的兩撓性電路(20)，各撓性電路(20)係與一封裝(10)相關聯，且該等撓性電路定位於該兩封裝之間，各撓性電路(20)包含：○在一面(21)上，面對該相關聯封裝之該等輸出球(13)的第一電性互連墊(22)；○在其端部，折疊於該相關聯封裝之一橫向面(16)上方的一部分(26)；○在此折疊部分(26)之該相對面上的第二電性互連墊(24)。

Abstract in simplified Chinese: 本发明关于一种3D电子模块(100)，其包含：- 两个经电性测试的电子封装(10)，各包含至少一封装芯片(11)与输出球(13)于该封装的一单一面上，该单一面称为该主要面(15)；- 彼此机械性连接的两挠性电路(20)，各挠性电路(20)系与一封装(10)相关联，且该等挠性电路定位于该两封装之间，各挠性电路(20)包含：○在一面(21)上，面对该相关联封装之该等输出球(13)的第一电性互连垫(22)；○在其端部，折叠于该相关联封装之一横向面(16)上方的一部分(26)；○在此折叠部分(26)之该相对面上的第二电性互连垫(24)。

公开(公告)号：TWI392054B

公开(公告)日：2013-04-01

申请号：TW096130739

申请日：2007-08-20

Applicant: 3D波拉斯公司 ,  3D PLUS

Inventor： 克里斯汀 佛 ,  VAL, CHRISTIAN

IPC: H01L21/70 ,  H01L21/66 ,  H01L25/065 ,  B81C1/00

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/1461 ,  Y10T29/49004 ,  H01L2924/00

公开(公告)号：TWI497686B

公开(公告)日：2015-08-21

申请号：TW099119295

申请日：2010-06-14

Applicant: 3D波拉斯公司 ,  3D PLUS

Inventor： 佛 克里斯汀 ,  VAL, CHRISTIAN

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

公开(公告)号：US11594972B2

公开(公告)日：2023-02-28

申请号：US17342487

申请日：2021-06-08

Applicant: 3D PLUS

Inventor： Cédric Colonna

IPC: H02M3/335 ,  H02M1/00 ,  H02M3/337

Abstract: A power converter having a parallel resonant circuit, includes an inverter, a resonant circuit, a transformer comprising a primary circuit and a secondary circuit, control means for the inverter, the inverter being connected to the resonant circuit, which is intended to be connected to an output load via the transformer, the power converter wherein the inverter comprises a first half-bridge and a second half-bridge in parallel with the first half-bridge, a first inductor between the first half-bridge and the resonant circuit, a second inductor between the second half-bridge and the resonant circuit, and in that the first and second inductors have the same inductance and are coupled in the opposite direction to one another.

公开(公告)号：US20180012520A1

公开(公告)日：2018-01-11

申请号：US15631863

申请日：2017-06-23

Applicant: SOLUTION 3D PLUS INC.

Inventor： Michel Cournoyer

IPC: G09F3/02 ,  F16B1/00

CPC classification number: G09F3/02 ,  F16B1/0071 ,  G09F2003/0214 ,  G09F2003/0216 ,  G09F2003/0272

Abstract: The present invention relates to label, device, system and method for sorting bolts, bars, pins, studs, dowels, screws or the like (collectively and individually described herein as a bolt). The bolts are being characterized by a first and a second dimension. The identification system comprises a color chart defining all ten numerals and most commonly used bolt diameters corresponding to various colors and an identification label. The identification label comprises a main section and at least one other section being both adapted to receive at least one color and/or a numeral. Each combination of a color and a numeral being defined by the color chart. The combination of colors and/or numerals of the main section defines the first dimension of the bolt and the combination of colors and/or numerals of the at least one other section defines the second dimension of the bolt.