公开(公告)号：US09899250B2

公开(公告)日：2018-02-20

申请号：US15621908

申请日：2017-06-13

Applicant: 3D PLUS

Inventor： Christian Val

IPC: H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H05K3/32

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/142 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K3/321 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages, several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers, dicing of the stacked reconstituted wafers to obtain 3D modules.

公开(公告)号：US11587911B2

公开(公告)日：2023-02-21

申请号：US17240789

申请日：2021-04-26

Applicant: 3D PLUS

Inventor： Christian Val

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00

Abstract: The field of the invention is that of producing 3D electronic modules, compatible with components operating beyond 1 GHz. The invention relates to a 3D electronic module featuring an interconnection between a horizontal conductor and a vertical conductor to which it is connected exhibits, in a vertical plane, a non-zero curvature. It also relates to the associated production process.

公开(公告)号：US10332863B2

公开(公告)日：2019-06-25

申请号：US16077968

申请日：2017-02-14

Applicant: 3D PLUS

Inventor： Christian Val

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/16 ,  H01L23/538 ,  H01L25/00

Abstract: The invention relates to a 3D electronic module including, in a direction referred to as the vertical direction, a stack (4) of electronic dice (16), each die including at least one chip (1) provided with interconnect pads (10), this stack being attached to an interconnect circuit (2) for the module provided with connection bumps, the pads (10) of each chip being connected by electrical bonding wires (15) to vertical buses (41) that are themselves electrically linked to the interconnect circuit (2) for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, characterized in that each electrical bonding wire (15) is linked to its vertical bus (41) by forming, in a vertical plane, an oblique angle (α2) and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another die and the corresponding vertical bus, and this is obtained by wiring the bonding wire in a non-rectilinear manner to compensate for the difference in vertical length of the vertical bus from one die to the other, such that the electrical conductor between the pad of a chip of one die and the interconnect circuit, and the electrical conductor between said same pad of a chip of the other die and the interconnect circuit, are the same length.

公开(公告)号：US10064278B2

公开(公告)日：2018-08-28

申请号：US15190837

申请日：2016-06-23

Applicant: 3D PLUS

Inventor： Christian Val

IPC: H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H05K1/18 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5387 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/00 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/73253 ,  H05K1/147 ,  H05K1/189

Abstract: A 3D electronic module comprises: two electrically tested electronic packages, each comprising at least one encapsulated chip and output balls on a single face of the package, referred to as the main face; two flexible circuits that are mechanically connected to one another, each being associated with a package, and which are positioned between the two packages, each flexible circuit comprising: on one face, first electrical interconnect pads facing the output balls of the associated package; at its end, a portion that is folded over a lateral face of the associated package; second electrical interconnect pads on the opposite face of this folded portion.

公开(公告)号：US08716036B2

公开(公告)日：2014-05-06

申请号：US13730047

申请日：2012-12-28

Applicant: 3D Plus

Inventor： Christian Val

IPC: H01L21/00

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/50 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24141 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/225 ,  H05K3/4688 ,  H05K2201/09981 ,  H05K2201/10674 ,  H05K2203/1327 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, molding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules.

Abstract translation: 一种用于3D电子模块的集体制造的方法包括：制造重叠的晶片堆叠，其包括验证的有源元件，该叠层包括再分布层; 制造经验证的无源印刷电路板，其包括：制造印刷电路板，每个印刷电路的电气测试，将经验证的印刷电路装配到粘合剂基板上，将电路中的安装电路模制成电绝缘树脂， 所谓的涂布树脂和树脂的聚合，去除粘合剂基材，仅由验证的印刷电路构成的面板被获得; 用叠层（重构晶片）粘合面板; 为了获得3D电子模块，切割“堆叠”面板组件。