公开(公告)号：WO2010144282A1

公开(公告)日：2010-12-16

申请号：PCT/US2010/037029

申请日：2010-06-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  BEDELL, Stephen, W. ,  SOSA CORTES, Norma ,  FOGEL, Keith, E. ,  SADANA, Devendra ,  SHAHIDI, Ghavam ,  SHAHRJERDI, Davood

Inventor： BEDELL, Stephen, W. ,  SOSA CORTES, Norma ,  FOGEL, Keith, E. ,  SADANA, Devendra ,  SHAHIDI, Ghavam ,  SHAHRJERDI, Davood

IPC: H01L31/06

CPC classification number: H01L31/0304 ,  H01L21/20 ,  H01L21/76254 ,  H01L31/03762 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  H01L31/20 ,  Y02E10/548

Abstract: A method for forming a heterojunction III-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a III-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer. A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.

Abstract translation: 用于形成异质结III-V光伏（PV）电池的方法包括从III-V衬底的晶片执行基底层的层转移，所述基底层小于约20微米厚; 在基层上形成本征层; 在本征层上形成非晶硅层; 以及在所述非晶硅层上形成透明导电氧化物层。 异质结III-V光伏（PV）电池包括包含III-V衬底的基层，所述基层小于约20微米厚; 位于基层上的本征层; 位于本征层上的非晶硅层; 以及位于非晶硅层上的透明导电氧化物层。

公开(公告)号：WO2010144202A1

公开(公告)日：2010-12-16

申请号：PCT/US2010/034161

申请日：2010-05-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  BEDELL, Stephen W. ,  SOSA CORTES, Norma ,  FOGEL, Keith E. ,  SADANA, Devendra ,  SAENGER, Katherine L. ,  SHAHRJERDI, Davood

Inventor： BEDELL, Stephen W. ,  SOSA CORTES, Norma ,  FOGEL, Keith E. ,  SADANA, Devendra ,  SAENGER, Katherine L. ,  SHAHRJERDI, Davood

IPC: H01L31/0352

CPC classification number: H01L31/0735 ,  H01L21/02002 ,  H01L31/0304 ,  H01L31/03046 ,  H01L31/0725 ,  H01L31/1808 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1892 ,  Y02E10/544 ,  Y02P70/521

Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes forming a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the largest bandgap being located on the substrate to the junction having the smallest bandgap being located on top of the stack; forming a metal layer, the metal layer having a tensile stress, on top of the junction having the smallest bandgap; adhering a flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the metal layer.

Abstract translation: 一种制造多结光伏（PV）电池的方法包括在衬底上形成包括多个结的叠层，所述多个结中的每一个具有相应的带隙，其中所述多个结从具有最大带隙的结点排序 位于具有最小带隙位于堆叠顶部的基底上的结点上; 在具有最小带隙的结的顶部上形成具有拉伸应力的金属层; 将柔性基板粘附到金属层上; 并且在基板的断裂处从基板剥离半导体层，其中响应于金属层中的拉伸应力而形成断裂。

公开(公告)号：WO2010016956A1

公开(公告)日：2010-02-11

申请号：PCT/US2009/041506

申请日：2009-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DE SOUZA, Joel, P. ,  HOVEL, Harold, John ,  INNS, Daniel, A. ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam, G.

Inventor： DE SOUZA, Joel, P. ,  HOVEL, Harold, John ,  INNS, Daniel, A. ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam, G.

IPC: H01L21/322

CPC classification number: H01L21/3225 ,  H01L21/02032

Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200°C or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.

Abstract translation: 描述了一种用于改善其中具有金属污染物的含硅晶片的少数寿命的方法，其包括在1200℃或更高温度下退火并提供氧气，惰性气体和含氯气体如HCl的气态环境。

公开(公告)号：WO2009056478A2

公开(公告)日：2009-05-07

申请号：PCT/EP2008064272

申请日：2008-10-22

Applicant: IBM ,  BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

Inventor： BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

IPC: H01L21/762

CPC classification number: H01L21/76245 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

Abstract: A method of fabricating a strained semiconductor-on- insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

Abstract translation: 提供一种制造应变半导体绝缘体（SSOI）衬底的方法。 该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。 在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。 接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。 在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

公开(公告)号：WO2006116098A3

公开(公告)日：2008-10-30

申请号：PCT/US2006015107

申请日：2006-04-21

Applicant: IBM ,  DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: In the claimed mixed-crystal-orientation channel FET, source/drain regions above the bonded interface 360 have the orientation of the upper semiconductor 350 and source/drain regions below the bonded interface 360 have the orientation of the lower semiconductor 370, so that each part of the source/drain has the same crystal orientation as the semiconductor material laterally adjacent to it. Optional source/drain extensions 392 are disposed entirely in the upper semiconductor layer 350. Optionally, the bonded interface 360 is situated towards the bottom of source/drain regions 380, leaving source/drains 380 mostly in upper semiconductor layer 350.

Abstract translation: 在所要求的混晶取向沟道FET中，键合界面360上方的源极/漏极区域具有上部半导体350的取向，并且键合界面360下方的源极/漏极区域具有下部半导体370的取向，使得每个 源极/漏极的一部分具有与横向相邻的半导体材料相同的晶体取向。 可选的源极/漏极延伸部分392完全设置在上部半导体层350中。可选地，接合界面360朝向源极/漏极区域380的底部设置，使得源极/漏极380大部分在上部半导体层350中。

公开(公告)号：WO2005043614A3

公开(公告)日：2005-11-03

申请号：PCT/EP2004052704

申请日：2004-10-28

Applicant: IBM ,  IBM UK ,  CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

Inventor： CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L27/14

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了用于制造绝缘体上锗（GOI）衬底材料的方法，通过该方法制造的GOI衬底材料以及可以包括至少本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶上的掩埋绝缘体层以及位于掩埋绝缘体层顶上的含Ge层，优选纯Ge。 在本发明的GOI基板材料中，含Ge层也可以被称为GOI膜。 GOI膜是其中可以形成器件的本发明衬底材料的层。

公开(公告)号：WO2005034209A3

公开(公告)日：2005-05-19

申请号：PCT/US2004031823

申请日：2004-09-28

Applicant: IBM ,  CHOE KWANG SU ,  FOGEL KEITH E ,  MAURER SIEGFRIED L ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

Inventor： CHOE KWANG SU ,  FOGEL KEITH E ,  MAURER SIEGFRIED L ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/265 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/762 ,  H01L21/20

CPC classification number: H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract translation: 提供了一种制造在含Si的上层下方具有薄但均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。 通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。 接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。 然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。

公开(公告)号：WO2004112102A3

公开(公告)日：2005-02-24

申请号：PCT/US2004016747

申请日：2004-05-27

Applicant: BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  MURPHY RICHARD J ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  MURPHY RICHARD J ,  SADANA DEVENDRA K

IPC: C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/324 ,  H01L21/477 ,  H01L21/762 ,  H01L27/01

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer (16) on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320°C for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

Abstract translation: 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层（12）上存在的第一单晶Si层（14）的表面上形成含Ge层（16）。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化方法，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

公开(公告)号：WO2004112102A2

公开(公告)日：2004-12-23

申请号：PCT/US2004/016747

申请日：2004-05-27

Applicant: BEDELL, Stephen, W. ,  CHEN, Huajie ,  DOMENICUCCI, Anthony, G. ,  FOGEL, Keith, E. ,  MURPHY, Richard, J. ,  SADANA, Devendra, K.

Inventor： BEDELL, Stephen, W. ,  CHEN, Huajie ,  DOMENICUCCI, Anthony, G. ,  FOGEL, Keith, E. ,  MURPHY, Richard, J. ,  SADANA, Devendra, K.

IPC: H01L21/00

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is proveded. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320°C for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

Abstract translation: 证明了形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并延迟整个第一单晶Si层和含Ge层的Ge的形成，从而在基底上形成基本上松弛的单晶SiGe层 阻挡层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化方法，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。