公开(公告)号：US20150145077A1

公开(公告)日：2015-05-28

申请号：US14554473

申请日：2014-11-26

Applicant: STMicroelectronics (Malta) Ltd

Inventor： Conrad Cachia ,  Kenneth Fonk

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0074 ,  B81C1/0023 ,  B81C3/001 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/27005 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48229 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83211 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/161 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/27 ,  H01L21/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of stacking a plurality of first dies to a respective plurality of second dies, each one of the first dies having a surface including a surface coupling region which is substantially flat, each one of the second dies having a respective surface including a respective surface coupling region which is substantially flat, the method comprising the steps of: forming, by means of a screen printing technique, an adhesive layer on the first dies at the respective surface coupling regions; and arranging the surface coupling region of each second die in direct physical contact with a respective adhesive layer of a respective first die among said plurality of first dies.

Abstract translation: 一种将多个第一管芯堆叠到相应的多个第二管芯的方法，每个第一管芯具有包括基本平坦的表面结合区域的表面，每个第二管芯具有包括相应表面的相应表面 该方法包括以下步骤：通过丝网印刷技术在相应的表面耦合区域上形成在第一裸片上的粘合剂层; 并且每个第二管芯的表面耦合区域与所述多个第一管芯中相应的第一管芯的相应的粘合剂层直接物理接触。

公开(公告)号：US20240132340A1

公开(公告)日：2024-04-25

申请号：US17973084

申请日：2022-10-24

Applicant: STMicroelectronics (Malta) Ltd.

Inventor： Roseanne DUCA

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/492 ,  H01L25/00 ,  H01L25/065

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H01L21/4875 ,  H01L23/4924 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/096 ,  B81C2203/038 ,  B81C2203/0771 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/167

Abstract: A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.

公开(公告)号：US20200185288A1

公开(公告)日：2020-06-11

申请号：US16788627

申请日：2020-02-12

Applicant: STMicroelectroncis (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd

Inventor： Jerome LOPEZ ,  Roseanne DUCA

IPC: H01L23/10 ,  H01L23/498 ,  H01L21/50 ,  H01L23/31

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.

公开(公告)号：US10435290B2

公开(公告)日：2019-10-08

申请号：US15725190

申请日：2017-10-04

Applicant: STMICROELECTRONICS (MALTA) LTD

Inventor： Conrad Cachia ,  David Oscar Vella ,  Damian Agius ,  Maria Spiteri

IPC: B81B7/00 ,  B81C1/00 ,  H01L23/00 ,  H01L23/31

Abstract: A MEMS device having a wafer-level package, is provided with: a stack of a first die and a second die, defining at least a first internal surface internal to the package and carrying at least an electrical contact pad, and at least a first external surface external to the package and defining a first outer face of the package; and a mold compound, at least in part coating the stack of the first and second dies and having a front surface defining at least part of a second outer face of the package, opposite to the first outer face. The MEMS device is further provided with: at least a vertical connection structure extending from the contact pad at the first internal surface towards the front surface of the mold compound; and at least an external connection element, electrically coupled to the vertical connection structure and exposed to the outside of the package, at the second outer face thereof.

公开(公告)号：US10357964B2

公开(公告)日：2019-07-23

申请号：US15917231

申请日：2018-03-09

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (MALTA) LTD

Inventor： Simon Dodd ,  Ivan Ellul ,  Christopher Brincat

IPC: B41J2/14 ,  B41J2/01 ,  B41J2/045

Abstract: One or more embodiments are directed to a microfluidic assembly that includes an interconnect substrate coupled to a microfluidic die. In one embodiment, the microfluidic die includes a ledge with a plurality of bond pads. The microfluidic assembly further includes an interconnect substrate having an end resting on the ledge proximate the bond pads. In another embodiment, the interconnect substrate abuts a side surface of the ledge or is located proximate the ledge. Conductive elements couple the microfluidic die to contacts of the interconnect substrate. Encapsulant is located over the conductive elements, the bond pads, the contacts.

公开(公告)号：US10329143B2

公开(公告)日：2019-06-25

申请号：US14977465

申请日：2015-12-21

Applicant: STMicroelectronics (Malta) Ltd

Inventor： Kevin Formosa

IPC: B81B7/00 ,  B81C1/00 ,  H04R31/00 ,  H04R19/00 ,  H04R19/04

Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.

公开(公告)号：US09802813B2

公开(公告)日：2017-10-31

申请号：US14860157

申请日：2015-09-21

Applicant: STMICROELECTRONICS (MALTA) LTD

Inventor： Conrad Cachia ,  David Oscar Vella ,  Damian Agius ,  Maria Spiteri

IPC: H01L29/84 ,  B81B7/00 ,  B81C1/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: B81B7/007 ,  B81B2207/098 ,  B81C1/00301 ,  B81C2203/0154 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2924/00012 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A MEMS device having a wafer-level package, is provided with: a stack of a first die and a second die, defining at least a first internal surface internal to the package and carrying at least an electrical contact pad, and at least a first external surface external to the package and defining a first outer face of the package; and a mold compound, at least in part coating the stack of the first and second dies and having a front surface defining at least part of a second outer face of the package, opposite to the first outer face. The MEMS device is further provided with: at least a vertical connection structure extending from the contact pad at the first internal surface towards the front surface of the mold compound; and at least an external connection element, electrically coupled to the vertical connection structure and exposed to the outside of the package, at the second outer face thereof.

公开(公告)号：US09620438B2

公开(公告)日：2017-04-11

申请号：US14615673

申请日：2015-02-06

Applicant: STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.l. ,  STMicroelectronics Pte Ltd

Inventor： Roseanne Duca ,  Valter Motta ,  Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/02 ,  H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/18301 ,  H01L2924/00014

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

公开(公告)号：US12148628B2

公开(公告)日：2024-11-19

申请号：US17942843

申请日：2022-09-12

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (MALTA) Ltd

Inventor： Roseanne Duca ,  Dario Paci ,  Pierpaolo Recanatini

IPC: H01L21/324 ,  H01L23/16 ,  H01L23/31

Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

公开(公告)号：US20240038610A1

公开(公告)日：2024-02-01

申请号：US18355966

申请日：2023-07-20

Applicant: STMICROELECTRONICS (MALTA) LTD

Inventor： Roseanne DUCA

IPC: H01L23/29 ,  H01L23/053 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/296 ,  H01L23/053 ,  H01L24/48 ,  H01L25/0655 ,  H01L21/561 ,  H01L25/50 ,  H01L24/85 ,  H01L2224/48225 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73265 ,  H01L24/73 ,  H01L2224/85

Abstract: A method of manufacturing a semiconductor package with an one or more dice present within a transparent resin, which may be an epoxy-based transparent resin or a silicone-based transparent resin, includes coupling the one or more dice to respective surfaces of a plurality of base portions of a panel substrate. Each one of the respective surfaces is between ones of a plurality of walls of the panel substrate that protrude from the respective surfaces of the panel substrate. A plurality of wirebonds may be formed to provide electrical pathways between the one or more dice and conductive structures of the panel substrate accessible at the respective surfaces of the panel substrate. A transparent resin may be formed to fill recesses or cavities between ones of the plurality of walls, and the panel substrate may then be singulated along the plurality of walls.