公开(公告)号：EP1638210A1

公开(公告)日：2006-03-22

申请号：EP04077551.2

申请日：2004-09-15

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc ,  Goetschalckx, Paul ,  Monterastelli, Andrea

IPC: H04B1/04 ,  H03D7/16 ,  H03C3/40

CPC classification number: H03J1/005 ,  H04B2001/0491

Abstract: An RF transmitter suitable for ISM band transmissions has an IF modulator (120) and an RF modulator (150), the IF modulator being arranged to use a very-low-IF-frequency f IF , smaller than half the channel bandwidth, such that spurious unwanted modulation components fall in other channels having a channel number within one or two of a channel being transmitted. This can reduce the VCO pulling problem and reduce adjacent channel power degradation compared to using higher IF frequencies. The local oscillator PLL's fractionality is used in order to optimize the adjacent power frequency plan by selecting the most appropriate IF frequency. For the "Bluetooth ® Wireless Technology" application, the IF frequency is

Abstract translation: 适用于ISM频带传输的RF发射机具有IF调制器（120）和RF调制器（150），IF调制器被配置为使用小于信道带宽一半的非常低的IF频率f IF，使得 杂散的不需要的调制分量落在其它信道中，其中信道号正在传输的信道的一个或两个之内。 与使用较高的IF频率相比，这可以减少VCO牵引问题并降低相邻信道功率的降低。 使用本地振荡器PLL的分数，以通过选择最合适的IF频率来优化相邻功率频率计划。 对于“蓝牙®无线技术”应用，IF频率<500kHz，主要无滤波杂散分量（1LO.xBB，x：-3，-2，...，+ 3）图像，载波， 对于0和1个FM信号，拉动被定位在相邻信道的频带中。

公开(公告)号：EP1422826B1

公开(公告)日：2006-02-22

申请号：EP02447227.6

申请日：2002-11-21

Applicant: STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/18 ,  H03L7/099 ,  H03L7/089

CPC classification number: H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

公开(公告)号：EP1596266A1

公开(公告)日：2005-11-16

申请号：EP04447121.7

申请日：2004-05-14

Applicant: STMicroelectronics Belgium N.V.

Inventor： Himpe, Vincent

IPC: G05F1/56

CPC classification number: G05F1/571

Abstract: The present invention is related to a regulator circuit comprising a regulator circuit input and a regulator circuit output, a regulating element in connection with the regulator circuit input and the regulator circuit output, and a control circuit arranged for being fed with a signal related to the regulator circuit output. The regulator circuit further comprises a safety detector arranged for being fed with the signal related to the regulator circuit output. The safety detector is further arranged to control a switch, being in connection with the control circuit's output and with the regulating element.

Abstract translation: 本发明涉及一种调节器电路，其包括调节器电路输入和调节器电路输出，与调节器电路输入和调节器电路输出相关的调节元件，以及控制电路，被配置为馈送与 稳压电路输出。 调节器电路还包括安全检测器，安全检测器被布置为馈送与调节器电路输出相关的信号。 安全检测器还被布置成控制与控制电路的输出和调节元件相关的开关。

公开(公告)号：EP1548932A1

公开(公告)日：2005-06-29

申请号：EP03079182.6

申请日：2003-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Joos, Dieter ,  Borremans, Marc

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/189 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45306 ,  H03F2203/45318

Abstract: A low noise differential amplifier has a pair of single ended common-gate or common-base circuits and cross coupling of an input of one of the pair to the gate or base of the other one of the pair. This cross-coupling puts the differential input voltage over the Gate-Source of the common-gate transistor (or Base-Emitter of the common base transistor). This means that the same input impedance and gain can be made with half the current compared to a basic common-gate topology. The cross-coupling means the noise generated by the positive side of the common-gate structure ends up partly on the negative output and vice versa, and so the Noise Figure can be less than 3dB.

Abstract translation: 低噪声差分放大器具有一对单端公共栅极或公共基极电路，并且该对中的一个的输入与该对中的另一个的栅极或基极交叉耦合。 这种交叉耦合将差分输入电压放在公共栅极晶体管（或公共基极晶体管的基极 - 发射极）的栅极 - 源极上。 这意味着与基本公共门拓扑相比，可以以一半的电流进行相同的输入阻抗和增益。 交叉耦合意味着由共栅结构的正侧产生的噪声部分地在负输出端反而相反，因此噪声系数可以小于3dB。

公开(公告)号：EP1545007A1

公开(公告)日：2005-06-22

申请号：EP04447281.9

申请日：2004-12-17

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC) ,  STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/081 ,  H03D3/00 ,  H03B27/00

CPC classification number: H03B27/00 ,  H03D7/18 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/16

Abstract: The present invention is related to a device for generating signals spaced π/X rad apart (X being an integer) comprising

at least one delay cell (15) with a delay approximately corresponding to a phase shift π/X rad, and
at least one phase detection system (16) inputting at least two signals (10) delayed by π/2 rad with respect to one another by the delay cell(s) (15) and generating a feedback signal (18) to at least one delay cell (15).

Abstract translation: 本发明涉及用于产生间隔π/ X辐射（X是整数）的信号的装置，该装置包括延迟大约对应于相移π/ X弧的至少一个延迟单元（15），以及至少一个 相位检测系统（16）通过延迟单元（15）相对于彼此输入延迟π/ 2弧度的至少两个信号（10）并且产生反馈信号（18）到至少一个延迟单元 15）。

公开(公告)号：EP1536599A1

公开(公告)日：2005-06-01

申请号：EP03078716.2

申请日：2003-11-26

Applicant: STMicroelectronics Belgium N.V.

Inventor： Van Parys, Jorgen

IPC: H04L12/56

CPC classification number: H04W74/04 ,  H04W74/06 ,  H04W84/18 ,  Y02D70/144 ,  Y02D70/25

Abstract: A Bluetooth master radio frequency unit (20) addresses a slave radio frequency unit, to enable the slave to resynchronize to the master, by sending poll packets or null packets, the master being arranged to send sufficient null packets to enable the slave to resynchronize, before sending a poll packet, to determine whether the slave has resynchronized. This approach can provide the slave with the same number of synchronization packets as in the simpler algorithms, while allowing the slave to preserve more (transmit) power and still allowing the master to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer for example). Notably this is also suitable for use in prescheduling implementations.

Abstract translation: 蓝牙主机射频单元（20）寻址从射频单元，以使从机能够通过发送轮询分组或空分组来重新同步主机，主机被安排为发送足够的空分组以使从机重新同步， 在发送轮询数据包之前，确定从站是否已重新同步。 这种方法可以为从属设备提供与更简单的算法相同数量的同步数据包，同时允许从器件保留更多（发送）功率，并且还允许主器件检测从器件是否已重新同步（从而更新 Link监控定时器）。 值得注意的是，这也适用于预调节实现。

公开(公告)号：EP1531591A1

公开(公告)日：2005-05-18

申请号：EP03078543.0

申请日：2003-11-11

Applicant: STMicroelectronics Belgium N.V.

Inventor： Aerts, Wouter ,  Hug, Roland

IPC: H04L27/26 ,  H04L27/38

CPC classification number: H04L27/2657 ,  H04L27/3881

Abstract: A signal resampler carries out a time domain interpolation of an input signal for compensating for frequency offset, such as found in an ADSL system. A sample selector interpolator carries out part of the interpolation and a second, e.g. polynomial interpolator carries out the rest of the interpolation. The time interval between samples being interpolated, can be effectively divided between sample selector interpolator and a small second, e.g. polynomial interpolator. The complexity of the second, e.g. polynomial interpolator can be reduced or its accuracy increased if it is effectively interpolating over a much smaller time interval. The sample selector interpolator can be an oversampling arrangement, and enable the order of the second, e.g. polynomial interpolator to be reduced. Selected ones of the oversampled samples are fed to the second, e.g. polynomial interpolator to keep the operating frequency lower. A chain of upsamplers can be used to generate the oversampled samples.

Abstract translation: 信号重采样器执行输入信号的时域内插以补偿频偏，例如在ADSL系统中发现的。 采样选择器内插器执行一部分内插，而第二个例如内插器执行内插。 多项式内插器执行其余的内插。 被插值的样本之间的时间间隔可以在样本选择器内插器与小的秒之间有效地分配。 多项式插值器。 第二个的复杂性，例如 多项式内插器如果在更小的时间间隔内进行有效内插，则可以减少或提高其精度。 采样选择器内插器可以是一个过采样装置，并且可以启用第二个采样选择器的顺序。 多项式内插器被减少。 将选定的一些过采样样本馈送到第二个例如 多项式内插器保持工作频率更低。 一系列上采样器可用于生成过采样采样。

公开(公告)号：EP1489521A1

公开(公告)日：2004-12-22

申请号：EP03447153.2

申请日：2003-06-16

Applicant: STMicroelectronics Belgium N.V.

Inventor： Levy, David

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1093 ,  G11C7/1006 ,  G11C7/1078

Abstract: The present invention is related to a method to control the access of two synchronous busses with asynchronous clocks with unknown relative speed to a single port Random Access Memory (RAM), comprising the steps of :

a) Providing a synchronisation system comprising two busses and a control flip-flop being clocked to the clock of one of said busses,
b) Providing a signal to said control flip-flop requesting a change of the clock of said RAM, resulting in a control flip-flop output signal,
c) Applying said control flip-flop output signal to an inverter circuit yielding a signal INV_out and to a circuit to synchronise said output signal to the clock of the bus not in control of said control flip-flop, yielding a signal CL_SW,
d) Applying the signal INV_out and the signal CL_SW each to a circuit to synchronise to the clock of the other bus yielding signals INV_out_SW and CL_SW_SW, respectively,
e) Applying the signal INV_OUT and the signal CL_SW_SW to a first combinatorial block outputting a signal en1_comb and applying the signal CL_SW and the signal INV_OUT_SW to a second combinatorial block outputting a signal en2_comb,
f) Applying the signal en1_comb and the signal en2_comb each to a falling edge sampling flip-flop, yielding signals en1 and en2, respectively,
g) Applying the signal en1 and the clock of the bus in control of said control flip-flop to an AND gate and the signal en2 and the clock of the other bus to an AND gate, and the outputs of said AND gates to an OR gate,
h) Using the output signal of said OR gate as the clock signal of said RAM
i) Applying the signals en1 and en2 to a combinatorial block that outputs the select signal selecting between said busses to the control and data multiplexers used for communication with said single port RAM.

Abstract translation: 本发明涉及一种用于控制具有与单端口随机存取存储器（RAM）的未知相对速度的异步时钟的两个同步总线的访问的方法，包括以下步骤：a）提供包括两个总线的同步系统和 控制触发器被计时到所述总线中的一个的时钟，b）向所述控制触发器提供请求改变所述RAM的时钟的信号，从而产生控制触发器输出信号，c）应用所述 控制触发器输出信号到逆变器电路，产生一个信号INV_out和一个电路，使所述输出信号与不在所述控制触发器的控制下的总线的时钟同步，产生信号CL_SW，d）应用信号INV_out 和信号CL_SW分别与电路同步的另一总线的时钟，分别产生信号INV_out_SW和CL_SW_SW，e）将信号INV_OUT和信号CL_SW_SW应用于第一组合块输出 信号en1_comb，并将信号CL_SW和信号INV_OUT_SW施加到输出信号en2_comb的第二组合块，f）分别将信号en1_comb和信号en2_comb应用于下降沿采样触发器，分别产生信号en1和en2， g）在所述控制触发器的控制中将信号en1和时钟施加到与门，并将信号en2和另一总线的时钟作为与门，将所述与门的输出连接到OR 门）h）使用所述OR门的输出信号作为所述RAM的时钟信号i）将信号en1和en2施加到组合块，该组合块将在所述总线之间选择的选择信号输出到用于与 表示单端口RAM。

公开(公告)号：EP1434401A1

公开(公告)日：2004-06-30

申请号：EP02447271.4

申请日：2002-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Pisoni, Fabio ,  Hug, Roland

IPC: H04L27/26 ,  H04L25/03

CPC classification number: H04L25/03159 ,  H04L25/03012 ,  H04L27/2647

Abstract: An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.

Abstract translation: 一种用于多载波传输系统的均衡器，将所发送的多载波信号转换为采样的频域信号，并对采样的频域信号抑制时域延迟色散。 它利用Toeplitz矩阵的循环分解，使得能够计算重估计矩阵乘以一个向量，以避免。 与通常实际相比，频域处理相当于更长时间的FIR滤波器产生的精度提高。 可以调整不同载体的补偿量，从而提高精度。

公开(公告)号：EP1638210B1

公开(公告)日：2009-05-06

申请号：EP04077551.2

申请日：2004-09-15

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc ,  Goetschalckx, Paul ,  Monterastelli, Andrea

IPC: H04B1/04 ,  H03D7/16 ,  H03C3/40

CPC classification number: H03J1/005 ,  H04B2001/0491