公开(公告)号：KR101156504B1

公开(公告)日：2012-06-18

申请号：KR1020110039902

申请日：2011-04-28

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 김대환 ,  정인영

IPC: G01R19/145 ,  G01N27/00

Abstract: PURPOSE: A device and a method for the calibration of a biosensor are provided to control the operation point of a biosensor by controlling bias voltage supplied to the biosensor. CONSTITUTION: A device(100) for the calibration of a biosensor comprises a biosensor unit(110), a comparison unit(120), a counter unit(130), and a Digital/Analog converter(140). The biosensor unit changes the conductivity of a semiconductor material. The comparison unit compares the output value from the biosensor unit with reference voltage. The counter unit controls a digital value outputted depending on the output value from the comparison unit. The D/A converter generates bias voltage corresponding to the digital value and supplies the bias voltage to the biosensor unit.

Abstract translation: 目的：提供一种用于校准生物传感器的装置和方法，用于通过控制提供给生物传感器的偏置电压来控制生物传感器的操作点。 构成：用于校准生物传感器的装置（100）包括生物传感器单元（110），比较单元（120），计数器单元（130）和数字/模拟转换器（140）。 生物传感器单元改变半导体材料的导电性。 比较单元将生物传感器单元的输出值与参考电压进行比较。 计数器单元控制根据比较单元的输出值输出的数字值。 D / A转换器产生对应于数字值的偏置电压，并将偏置电压提供给生物传感器单元。

公开(公告)号：KR101113990B1

公开(公告)日：2012-03-05

申请号：KR1020110110834

申请日：2011-10-27

Applicant: 국민대학교산학협력단

Inventor： 신자선 ,  김동명 ,  김대환

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/8242

Abstract: PURPOSE: A novel double HBT-based capacitorless 1t dram cell with Si/SiGE hetero junctions is provided to improve carrier production rate by forming a hetero structure which is divided into the upper part and lower part of a body. CONSTITUTION: A body(110) of a vertical pin type is formed on a substrate(100). The body is formed by using silicon-germanium. The source(120) and drain(130) of a silicon material are formed in right and left sides of the longitudinal direction of the body. A top gate(140) and a bottom gate(150) of a double structure are formed in the top and bottom of the body. A spacer(170) isolates the top gate, the bottom gate, the source and the drain.

Abstract translation: 目的：提供一种具有Si / SiGE异质结的新颖的基于HBT的双电池无电容器1t电池，通过形成分为机体上部和下部的异质结构来提高载流子生产率。 构成：在基板（100）上形成垂直销型的主体（110）。 身体通过使用硅 - 锗形成。 硅材料的源极（120）和漏极（130）形成在主体的纵向方向的左右两侧。 双体结构的顶门（140）和底门（150）形成在主体的顶部和底部。 间隔物（170）隔离顶栅，底栅，源极和漏极。

公开(公告)号：KR1020110126004A

公开(公告)日：2011-11-22

申请号：KR1020100045681

申请日：2010-05-14

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  김대환 ,  이순영 ,  장재만 ,  김효종 ,  신자선

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/78696 ,  H01L27/108 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/78684

Abstract: PURPOSE: An SBE EDRAM cell transistor which does not have a capacitor is provided to improve a charge holding characteristic by shutting a hole using band offset between a silicon germanium layer and a silicon layer. CONSTITUTION: A silicon dioxide obstacle(100) secludes that a hole which is created by impact ionization gets out. A pair of silicon source-drain layers(200) is formed in the upper end of the silicon dioxide obstacle. A silicon channel layer(300) is formed in order to be contiguous between a pair of silicon source-drain layers. A silicon germanium layer(400) is heterogeneously united in the bottom end of the silicon channel layer and stores the hole which is created by the impact ionization.

Abstract translation: 目的：提供不具有电容器的SBE EDRAM单元晶体管，以通过利用硅锗层和硅层之间的带偏移来关闭空穴来提高电荷保持特性。 构成：二氧化硅障碍物（100）隐藏通过冲击电离产生的孔出来。 在二氧化硅障碍物的上端形成一对硅源极 - 漏极层（200）。 形成硅沟道层（300）以便在一对硅源极 - 漏极层之间连续。 硅锗层（400）在硅沟道层的底端中非均匀地结合在一起，并存储由冲击电离产生的孔。

公开(公告)号：KR1020110006577A

公开(公告)日：2011-01-20

申请号：KR1020100002908

申请日：2010-01-12

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  김대환 ,  이순영

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/265 ,  H01L21/28282 ,  H01L21/31051 ,  H01L29/4234 ,  H01L29/792

Abstract: PURPOSE: A NOR type memory architecture using non-volatile memory cell is provided to improve the integration degree of memory integration and reduce the error which may occur durin data determining operation though an efficient arrangement of memory cell. CONSTITUTION: A first oxide film is formed on an active pin area of I shape for forming a source/drain area. A second oxide film is formed on the gate area shaped like T. A charge trapping layer is formed between the first oxide film and the second oxide film(S130). The arsenic ion is injected into the source/drain area for doping.

Abstract translation: 目的：提供使用非易失性存储单元的NOR型存储架构，以提高存储器集成的集成度，并通过存储单元的有效布置来减少在数据确定操作中可能发生的错误。 构成：第一氧化膜形成在I形的有源销区上，用于形成源/漏区。 第二氧化膜形成在类似T的栅区上。在第一氧化膜和第二氧化物膜之间形成电荷捕获层（S130）。 将砷离子注入源极/漏极区域进行掺杂。