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公开(公告)号：KR100384457B1
公开(公告)日：2003-05-22
申请号：KR1020000042666
申请日：2000-07-25
Applicant: 삼성전기주식회사
Inventor： 이대형
IPC: H01F27/245 , H01F27/26
Abstract: PURPOSE: A chip inductor is provided to prevent a degradation of a chip performance by minimizing an influence of a parasitic capacity caused by a distance reduction between an inner electrode and an outer electrode, and minimizes a chip volume by increasing an inner area of the electrode. CONSTITUTION: An inner electrode(100) is connected to many magnetic sheets(110) through a via-hole, and is screw-formed in a vertical direction of the magnetic sheet(110). An outer electrode(200) is formed only to both edge parts of the magnetic sheets(110) that connects between a starting point and an ending point of the inner electrode(100). The outer electrode(200) is formed to an edge part by a jig mounted to both sides of the chip inductor(300).
Abstract translation: 目的：提供芯片电感器以通过最小化由内部电极和外部电极之间的距离减小引起的寄生电容的影响并通过增加电极的内部面积来最小化芯片体积来防止芯片性能的劣化 。 构成：内部电极（100）通过通孔与许多磁性片（110）连接，并沿着磁性片（110）的垂直方向螺旋形成。 仅在连接内部电极（100）的起始点和终止点的磁性片（110）的两个边缘部分形成外部电极（200）。 外部电极（200）通过安装在芯片电感器（300）的两侧的夹具形成到边缘部分。
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公开(公告)号：KR1020030037747A
公开(公告)日：2003-05-16
申请号：KR1020010068603
申请日：2001-11-05
Applicant: 삼성전기주식회사
IPC: H03H7/01
CPC classification number: H01G4/35 , H01F17/0013 , H01F2017/0026 , H01L27/08 , H03H7/0115
Abstract: PURPOSE: A multi-noise filter is provided to minimize the electromagnetic interference by forming inductance portions with two coil portions and making the coil portions with different rotary directions. CONSTITUTION: A multi-noise filter is formed with two noise reduction filters. The multi-noise filter is formed by installing the first and the second noise reduction filters(20a,20b) inside of a single chip. Each of the first and the second noise reduction filters(20a,20b) has the first and the second earth portions(22,23), the first capacitance portion(24a,24b), the second capacitance portion(25a,25b), and an inductance portion. The first capacitance portion(24a,24b) is connected with the first earth portion(22) and an input terminal. The second capacitance portion(25a,25b) is connected with the second earth portion(23) and an output terminal. The inductance portion is connected with the input terminal and the output terminal. The inductance portion is formed with the first coil(27a',27b') and the second coil(27a",27b"). A conductive layer(29a,29b) is provided between the first coil(27a',27b') and the second coil(27a",27b").
Abstract translation: 目的：提供多噪声滤波器，通过形成具有两个线圈部分的电感部分并使线圈部分具有不同的旋转方向来最小化电磁干扰。 构成：使用两个降噪滤波器形成多噪声滤波器。 多噪声滤波器是通过将第一和第二降噪滤波器（20a，20b）安装在单个芯片内而形成的。 第一和第二降噪滤光器（20a，20b）中的每一个具有第一和第二接地部分（22,23），第一电容部分（24a，24b），第二电容部分（25a，25b）和 电感部分。 第一电容部（24a，24b）与第一接地部（22）和输入端子连接。 第二电容部（25a，25b）与第二接地部（23）和输出端子连接。 电感部分与输入端子和输出端子相连。 电感部分由第一线圈（27a'，27b'）和第二线圈（27a“，27b”）形成。 在第一线圈（27a'，27b'）和第二线圈（27a“，27b”）之间设置有导电层（29a，29b）。
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公开(公告)号：KR100349124B1
公开(公告)日：2002-08-17
申请号：KR1019990058901
申请日：1999-12-18
Applicant: 삼성전기주식회사
IPC: H05K3/00
Abstract: 본발명은핸드폰등에사용되는칩 부품으로분할기인스플리터(SPLITTER)에있어서, 스플리터의측면에단자전극을용이하게형성할수있도록한 칩부품제조방법에관한것으로서그 기술적인구성은, 일정패턴의내부전극이일체로형성되는세라믹시트부의적층에의한칩부품의형성시그 측면에마킹과상면단자전극및상면접지전극을일체로돌출인쇄하고, 상기단자전극과접지전극을내부전극과연결토록하는측면전극을칩블록의측면에인쇄하여칩부품을완성하는것을요지로한다.
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公开(公告)号：KR100320932B1
公开(公告)日：2002-04-17
申请号：KR1019980056530
申请日：1998-12-19
Applicant: 삼성전기주식회사
IPC: H03H7/075
Abstract: 본 발명은 LC회로용 복합재료 및 이를 이용한 EMI LC 필터 제조방법에 관한 것이며, 그 목적하는 바는 페라이트와 비자성체 재료를 적정비율로 하고 유리질의 첨가제를 사용함으로서, 기존의 방법에 의한 소성온도에 비해 낮은 소성온도를 갖도록 하여 전극을 형성한 후에 전극과 동시에 소성을 행할 수 있는 복합재료 및 이를 이용한 EMI LC 필터 제조방법을 제공하는데 있다.
상기 목적을 달성하기 위한 본 발명은 인덕터와 캐패시터 특성을 동시에 보이는 복합재료에 있어서, 20-80중량%의 Ni-Zn페라이트 또는 Ni-Zn-Cu페라이트와, 20-80중량%의 유전체 재료와, 상기 페라이트와 유전체재료의 중량에 대하여 10-30중량%의 비율을 갖는 유리가 함유되는 LC회로용 복합재료에 관한 것을 그 요지로 하며, 또한, 본 발명은 EMI LC 필터를 제조하는 방법에 있어서, 중량%로 Ni-Zn페라이트 또는 Ni-Zn-Cu페라이트를 20-80%, 유전체 재료를 20-80%의 비율로 하고, 여기에 상기 페라이트와 유전체재료의 중량에 대하여 10-30%의 유리를 혼합하는 단계; 상기 혼합물에 바인더를 첨가하여 슬러리 믹싱하고 시트상으로 제조하는 단계; 원하는 패턴에 알맞게 홀펀칭 및 인쇄한 후, 적층하는 단계; 및 850℃이상에서 소성을 행하는 단계를 포함하는 EMI LC 필터 제조방법에 관한 것을 그 요지로 한다.-
公开(公告)号：KR1020010057123A
公开(公告)日：2001-07-04
申请号：KR1019990058901
申请日：1999-12-18
Applicant: 삼성전기주식회사
IPC: H05K3/00
CPC classification number: H05K3/4629 , H01G4/2325 , H05K1/0306 , H05K3/0052
Abstract: PURPOSE: A method for manufacturing a chip component is provided to minimize variation in electric characteristic, form a precise terminal electrode and improve productivity. CONSTITUTION: A ground electrode(140), a marking(130) and a terminal electrode(150) are formed by a printing to be electrically separated from each other on the first ceramic sheet which is laminated and printed. An inside electrode(100) is formed such that both ends of the inside electrode is protruded to an upper surface on the second ceramic sheet which is laminated and printed on the first ceramic sheet. A chip block(120) is formed by forming the ground electrode and the terminal electrode on the third ceramic sheet which is laminated and printed on the second ceramic sheet. A lateral surface electrode(150) is formed by a printing to be connected at least a part of the terminal electrode which is formed on an upper surface of the chip block and to be connected at least a part of the inside electrode. The chip block is formed by cutting a green bar in a standard size.
Abstract translation: 目的：提供一种用于制造芯片部件的方法，以最小化电特性的变化，形成精确的端子电极并提高生产率。 构成：通过印刷形成接地电极（140），标记（130）和端子电极（150），以在层叠和印刷的第一陶瓷片上彼此电分离。 内部电极（100）形成为使得内部电极的两端突出到层叠并印刷在第一陶瓷片上的第二陶瓷片上的上表面。 通过在第二陶瓷片层叠印刷的第三陶瓷片上形成接地电极和端子电极来形成芯片块（120）。 侧表面电极（150）通过印刷形成，以连接形成在芯片块的上表面上并连接至内部电极的至少一部分的端子电极的至少一部分。 芯片块通过以标准尺寸切割绿色条形成。
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Patent Agency Ranking
公开(公告)号：KR1020150070810A
公开(公告)日：2015-06-25
申请号：KR1020130157437
申请日：2013-12-17
Applicant: 삼성전기주식회사
CPC classification number: H05K1/185 , G01R1/07378 , H01G4/12 , H01G4/224 , H05K3/4688 , H05K2201/10015 , H05K2201/10636 , Y02P70/611 , Y10T156/1064
Abstract: 캐패시터내장기판및 그제조방법이개시된다. 제1 회로를포함하는세라믹층; 상기세라믹층의일면에형성되는수용홈; 상기수용홈에삽입되는캐패시터(capacitor); 상기캐패시터가상기수용홈에내장되도록상기세라믹층상에적층되며, 상기제1 회로와전기적으로연결되는제2 회로를포함하는폴리머층; 및상기폴리머층을관통하여상기캐패시터와연결되는비아전극을포함하는캐패시터내장기판및 그제조방법이제공된다.
Abstract translation: 公开了电容器嵌入式基板及其制造方法。 电容器嵌入式基板包括：包括第一电路的陶瓷层; 形成在陶瓷层一侧的接收槽; 插入到所述接收槽中的电容器; 层叠在所述陶瓷层上以将所述电容器嵌入所述容纳槽的聚合物层，并且包括电连接到所述第一电路的第二电路; 以及穿过聚合物层并连接到电容器的通孔电极。
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公开(公告)号：KR1020130039462A
公开(公告)日：2013-04-22
申请号：KR1020110104022
申请日：2011-10-12
Applicant: 삼성전기주식회사
CPC classification number: G01R1/07307 , G01R3/00 , G01R31/2601
Abstract: PURPOSE: A probe card and a manufacturing method thereof are provided to improve the adhesion between a ceramic substrate and an electrode pad by burying the electrode pad in one surface of the ceramic substrate. CONSTITUTION: A circuit pattern(6) and an electrode pad(4) are formed on one surface of a ceramic substrate(10). The circuit pattern connects the electrode pad to a via electrode(2) connected to the inner part of the ceramic substrate. The electrode pad is separated from the ceramic substrate. A probe pin(20) includes a bonding part(13), a body part(15), and a contact part(17). One end of the bonding part is electrically connected to the electrode pad of the ceramic substrate.
Abstract translation: 目的：提供探针卡及其制造方法，以通过将电极焊盘埋入陶瓷基板的一个表面来改善陶瓷基板和电极焊盘之间的粘合性。 构成：在陶瓷基板（10）的一个表面上形成电路图案（6）和电极焊盘（4）。 电路图案将电极焊盘连接到连接到陶瓷衬底的内部的通孔电极（2）。 电极焊盘与陶瓷衬底分离。 探针（20）包括接合部（13），主体部（15）和接触部（17）。 接合部的一端与陶瓷基板的电极焊盘电连接。
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公开(公告)号：KR1020130015661A
公开(公告)日：2013-02-14
申请号：KR1020110077781
申请日：2011-08-04
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A multilayer ceramic substrate and manufacturing method thereof are provided to effectively prevent occurrence of inter-layer short by interposing an insulation layer between a first conductive pattern and a second conductive pattern on a ceramic sheet. CONSTITUTION: A multilayer ceramic substrate(100) consists of a ceramic laminate. The ceramic laminate consists of a plurality of ceramic sheets(100a-100d). The first conductive patterns(120a-120d) are formed in the ceramic sheet. The second conductive patterns(140a-140d) surround the first conductive patterns. Insulation patterns(160a-160d) are interposed between the first conductive patterns and the second conductive patterns.
Abstract translation: 目的：提供一种多层陶瓷基板及其制造方法，通过在陶瓷板上的第一导电图案和第二导电图案之间插入绝缘层，有效地防止层间短路的发生。 构成：多层陶瓷基板（100）由陶瓷层压板组成。 陶瓷层叠体由多个陶瓷片（100a-100d）组成。 第一导电图案（120a-120d）形成在陶瓷片中。 第二导电图案（140a-140d）围绕第一导电图案。 绝缘图案（160a-160d）插入在第一导电图案和第二导电图案之间。
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公开(公告)号：KR1020120095657A
公开(公告)日：2012-08-29
申请号：KR1020110015108
申请日：2011-02-21
Applicant: 삼성전기주식회사
CPC classification number: G01R1/07378 , G01R31/2601
Abstract: PURPOSE: An STF(Space Transformer) substrate is provided to prevent the separation of a via electrode by forming a top via and a bottom via in zigzag. CONSTITUTION: A plurality of laminated substrates are provided. A plurality of via holes(20) are formed on the substrate to conduct a circuit between substrates. An overlap region is formed between via holes. A via electrode(40) is filled in the via hole. A conductive catch pad is formed between the laminated via holes.
Abstract translation: 目的：提供STF（空间变压器）基板，以通过以曲折形成顶部通孔和底部通孔来防止通孔电极的分离。 构成：提供多个叠层基板。 在基板上形成多个通孔（20），以在基板之间导电。 在通孔之间形成重叠区域。 通路电极（40）填充在通孔中。 在层叠的通孔之间形成导电捕获垫。
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公开(公告)号：KR101079385B1
公开(公告)日：2011-11-02
申请号：KR1020090129224
申请日：2009-12-22
Applicant: 삼성전기주식회사
IPC: H05K1/02
CPC classification number: H05K1/0263
Abstract: 본발명에의한인쇄회로기판어셈블리는, 상면에다수의회로소자들이실장된인쇄회로기판; 상면에상기인쇄회로기판이실장되며, 전원라인수용부가형성되는하우징; 및상기전원라인수용부에실장되며, 상기회로소자들에전원을공급하는전원라인;을포함한다.
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