Abstract:
The present invention relates to a semiconductor test method comprising a step of generating a test input signal including test information; a step of obtaining a test output signal with regard to the test input signal; and a step of determining whether a glitch is generated based on the test information and the test output signal.
Abstract:
무선통신칩 성능 테스트 장치와 그 방법이 개시되며, 시험용 패킷을 전송하는 시험기; 및 상기 시험기에서 전송되는 패킷을 모뎀을 사용하여 복조하고, 테스트용 전용로직이 구비된 테스트 모드 제어부를 사용하여 오류율을 계산하여 상기 시험기로 출력하는 시험 대상 장치와 그 방법을 포함하며, 신속하게 무선통신칩을 테스트 할 수 있다. 무선통신칩, 수신 감도, PER, 에러율, 시험 대상 장치
Abstract:
PURPOSE: An apparatus for testing TX/RX performance of a communication device is provided to lower a test qualification by embodying a test device as low cost for TX/RX test of communication device. CONSTITUTION: A test controller(100) is provided with a TX performance test result by controlling TX performance text of communication device. The test controller is provided with a RX performance test result by controlling RX performance test of the communication device. A test unit(200) tests TX performance based on TX signal according to a TX performance test control of the test controller. The test unit transmits the TX performance test result to the test controller.
Abstract:
본 발명은 저전력모드를 갖는 시스템온칩에 관한 것으로, 정상모드시 메인 클럭 신호를 공급함과 함께, 아날로그 및 디지탈 파워 공급을 제어하며, 저전력모드시 서브 클럭 신호를 공급함과 함께, 아날로그 파워 오프를 제어하는 파워 파트; 상기 파워 파트의 제어에 따라 정상모드시 동작하여 메인 클럭신호를 생성하고, 저전력모드시 동작을 정지하는 RF 파트; 및 상기 파워 파트의 제어에 따라 정상모드시는 메인 클럭신호에 따라 동작하고, 저전력모드시는 서브 클럭신호에 따라 동작하는 제어 파트를 구비한다. 또한, 본 발명은, 상기 시스템온칩에 적용되는 구동방법도 제안한다. 저전력, 시스템온칩, 구동, 클럭, 파워, 레귤레이터
Abstract:
A radio frequency receiver which has a timing offset recovering function and a timing offset recovering method are provided to recover the timing offset by moving the location of a determination slot according to the offset of a sample signal generated through the signal sampling. A preprocessor(110) converts a radio frequency signal into a digital signal. A differential operation unit(120) obtains a differentiated signal by multiplying the digital signal by a received digital signal. A correlation unit(130) correlates the differentiated signal with each PN code sequence and sequentially outputs the correlated results. A setting unit(140) sequentially stores the correlation values. A demodulated value estimation unit(150) estimates the PN code sequences based on the symbol of the received signal.
Abstract:
A direct sequence spread spectrum transceiver using a differentiation detection type and an integrated and short code is provided to reduce the influence of frequency error by employing differentiation detection method in a receiver by using short code word. A DSSS transmission unit(100) is comprised of an integral code mapping unit(110) and an RF transmitter(120). An integral code mapping part maps one of source data set up with N bit. The mapped symbol is mapped among set up in advance integral coding words with one. It loads the RF carrier wave with the integral coding word mapped with the integral code mapping part and the RF transmitter transmits a message. A DSSS receiver(200) is comprised of the RF receiver(210), the differential circuit unit(220), and the symbol detection part(230). The RF carrier is removed in the RF receiver is the radio frequency signal from the RF transmitter. The analog signal removing RF carrier is converted into digital signal. The differential circuit unit differentiates the digital signal from the RF receiver. The symbol detection part detects with the symbol under the maximum correlation value among the correlation value between a plurality of standards coding word which is already set up from the differential circuit unit.
Abstract:
케이스와, 케이스의 내부에 고정되며 케이스의 이동을 인식하는 광 모듈과, 외부 장치와 연결되며 광 모듈에 의해 인식된 정보를 외부장치에 전달하고, 휴대용 저장장치를 구비하는 커넥터를 포함하고, 휴대용 저장장치는 메모리를 구비하여 메모리에 데이터를 저장하고, 저장된 데이터를 외부장치가 읽을 수 있는 정보 저장 및 입력장치는 정보의 입력은 물론 저장을 수행할 수 있기 때문에 휴대 및 사용이 편리하다. 메모리, USB, 커넥터
Abstract:
An SoC(System on Chip) having a low power mode and an operating method thereof are provided to reduce dynamic and static power consumption by including the low power mode, which cuts off a first clock/power and uses a second clock/power of a lower frequency than the first clock/power. A first regulator(110) supplies first power which is main power of an SoC(100). A first clock generator(120) generates a first clock which is a basic clock for operating the SoC. A first memory(150) stores data inputted/outputting to a CPU(130), a DMA(Direct Memory Access)(140), a peripheral device part(160), and a modem(170). A mode controller(180) operates the SoC in an active, idle, or stop mode according to a state of the SoC. A low power mode controller(190) is operated by a second clock of a lower frequency than the first clock and second power of a lower voltage level than the first power to operate the SoC in the low power mode according to the state of the SoC. The lower power mode controller includes a second regulator(191) for supplying the second power, an operation controller(193), a second memory(192), and a second clock generator(194).